The clock circuitry on the PXIe-5624 offers versatile clocking options with the ability to use either the internal phase-locked loop (PLL) circuit on the digitizer or to accept an external 2 GHz or 4 GHz ADC Clock that you provide. The PLL has the option of locking to an internal 40 MHz reference, the PXI Express 100 MHz reference or an external Reference Clock that you provide. The external reference is limited to frequencies of 10 MHz or 100 MHz. The following diagram shows the clocking options of the PXIe-5624.



ADC Clock

The ADC Clock is sent to the ADC and to the FPGA through dividers. The ADC Clock runs at a rate of 2 GHz. Digital signal processing on the FPGA provides the ability for digital decimation and fractional delay.

  • Onboard ADC Clock—The PXIe-5624 generates an ADC Clock by locking a 2 GHz oscillator to a 40 MHz temperature compensated crystal oscillator (TCXO) through a phase locked loop (PLL).
  • External ADC Clock—Some applications may require the use of an external ADC Clock. External clocking provides a method to synchronize the digitizer to other devices in a measurement system by distributing a common clock to multiple devices. An external ADC Clock can be supplied to the digitizer through the CLK IN front panel connector. Refer to the PXIe-5624 Specifications for external ADC Clock requirements. The external clock can be 2 GHz or 4 GHz. The PXIe-5624 divides a 4 GHz external clock by 2 before sending it to the ADC.

    • You can export the 2 GHz ADC Clock, which clocks the ADC, to the CLK OUT front panel connector. The signal power of the ADC Clock coming from CLK OUT is sufficient to allow a daisy chain distribution of a common ADC Clock to multiple digitizers. This provides a method for distributing a common clock for synchronization.

    Reference Clock

    The PLL circuit can lock the onboard ADC Clock to a Reference Clock. The digitizer can accept a Reference Clock from the CLK IN front panel connector as well as from PXIe_CLK100. Two reference frequencies are supported: 10 MHz and 100 MHz. The frequency stability of the ADC Clock will match that of the PLL Reference Clock when the two are phase locked. Phase locking aligns the phase of the ADC Clock of multiple devices that are phase locked to the same Reference Clock.

    If you are using an external Reference Clock to phase lock the internal ADC Clock, you can export the Reference Clock to the CLK OUT front panel connector for use with other instruments.