Process (VI)

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Updated2025-11-22
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Process (VI)

Manages the transfer of enqueued elements to and from the DRAM.

Place this VI inside a single cycle timed loop that uses a DRAM clock with a speed as close as possible to the DRAM clock speed that is optimal for the device. See the help for your FPGA target to identify which clock is optimal for its DRAM.

Process

DRAM FIFO Ref In specifies the reference to the DRAM FIFO.

write grant time (clock ticks) specifies the number of consecutive writes to perform to DRAM before switching back to reads. Longer grant times reduce the number of switches between reads and writes and are more efficient than shorter grant times.

read grant time (clock ticks) specifies the number of consecutive reads to perform from DRAM before switching back to writes. Longer grant times reduce the number of switches between reads and writes and are more efficient than shorter grant times.

dynamic arbitration specifies how to dynamically assign throughput to reads and writes.

None	Use the specified grant times for reads and writes.
Dynamic (priority write)	Ignore grant time inputs and dynamically allocate throughput to avoid overflows as long as possible.
Dynamic (priority read)	Ignore grant time inputs and dynamically allocate throughput to avoid underflows as long as possible.

reset in progress? indicates whether a reset is in progress.

status provides information on how full the DRAM is as well as how many elements are waiting to be read from the To DRAM queue and From DRAM queue.

	elements in 'to DRAM queue' indicates the number of elements in the To DRAM queue.
	elements in 'from DRAM queue' indicates how many elements are in the From DRAM queue.
	elements in DRAM indicates how many elements are in the DRAM.
	DRAM full indicates whether the DRAM is full.
	DRAM empty indicates whether the DRAM is empty.

FlexRIO API Reference

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Process (VI)