Use the DI Sample Clock (di/SampleClock) signal to sample digital I/O on any slot using parallel digital modules, and store the result in the DI waveform acquisition FIFO. If the cDAQ chassis receives a DI Sample Clock signal when the FIFO is full, it reports an overflow error to the host software.

A sample consists of one reading from each channel in the DI task. DI Sample Clock signals the start of a sample of all digital input channels in the task. DI Sample Clock can be generated from external or internal sources as shown in the following figure.

Figure 35. DI Sample Clock Timing Options

Routing DI Sample Clock to an Output Terminal

You can route DI Sample Clock to any output PFI terminal on an installed C Series module.