The Aurora links between the RTG VST and the coprocessor do not natively provide a deterministic latency for IQ data. This potentially causes errors in expected delay settings from coprocessor-supplied signals. To address this behavior, a buffering and initialization scheme is part of the VST implementation of Aurora.You must inform the VST of the desired round-trip latency for data that enters the VST Rx port and passes to the coprocessor before generating on the VST Tx port.

The buffering for this technique has limits. Specifying a minimum latency that is too low causes the buffers to underflow. Specifying a minimum latency that is too high causes the buffers to overflow. Call the Coprocessor Link Status VI to determine if there are underflows or overflows.

The value of this round-trip latency depends on the algorithm in the coprocessor. For example, the template is a simple loopback where input is directly connected to output with no additional processing clocks. Refer to the minimum latency settings in the following table:
Note In the following table, the RTG clock resolution is 6.4 ns. Every feedback node the data pass-thrus adds more latency. Find the number of clocks it takes output valid from the read function to make it to input valid on the write function. Each clock adds 6.4 ns to the minimum latency.
Table 34. RTG/Coprocessor Characteristics
RTG Coprocessor Sample Rate for Baseband Data Approximate Minimum Latency
PXIe-5830/5831/5832/5841 PXIe-6594 or PXIe-7903 1.25 GS/s ~2.7 µs
PXIe-5842 PXIe-7903 2.50 GS/s ~5.2 µs