Master Clock

The pattern execution engine, timing circuitry, and formatting circuitry on the digital pattern instrument run using a 100 MHz fixed master clock, MasterClk, which processes the data and places timing edges.

Phase Lock Loop (PLL) Reference

The onboard frequency generator on the digital pattern instrument uses a phase-locked loop (PLL) circuit to lock the MasterClk of the instrument to the 100 MHz chassis backplane reference signal, PXIe_CLK100.

Figure 18. Digital Pattern Instrument Clocking Architecture


Vector Periods

The time set specifies the vector period to use for pattern execution. You can modify vector periods on a vector-by-vector basis with the digital pattern instrument. Refer to the Digital Pattern User Manual for more information about specifying and loading time sets programmatically or through the Digital Pattern Editor.