For output devices, such as the NI 5421 arbitrary waveform generator and NI 6552 digital waveform generator/analyzer, the sequencing instructions are stored in the same physical memory as the waveforms. Traditional arbitrary waveform generators are based on architectures where instructions for sequencing waveforms are stored in physically separate SRAM memory comprised of a few kilobytes, which severely limits the maximum number of waveforms that can be sequenced. The SMC takes a unique, far-more-flexible approach by combining the instructions along with waveforms in the same physical memory so that you are not constrained by a very limited number of sequencing instructions. With memory configurations ranging up 256 MB, you have the flexibility to use as much memory as you need for sequencing instructions. A closer look at the arbitrary waveform generator sequencing specifications sheds some light on the flexibility of shared memory between waveforms and instructions as seen in the following tables.
A traditional arbitrary waveform generator (AWG) may feature the specifications for waveform memory and sequencing capabilities shown in Table 1.
The specifications shown in Table 1 are fixed for the traditional AWG. It cannot exceed 4,096 steps for a given sequence. The NI 5421 arbitrary waveform generator, with the standard memory of 8 MB, offers the flexible waveform memory and sequencing capabilities shown in Tables 2, 3, and 4 because of its shared memory format.
The scenarios shown in the previous tables are representative of what is achievable with shared waveform and instruction memory. With shared memory, you can use the memory space for very long sequences with small waveforms, short sequences with very large waveforms, or a balance in between. Furthermore, with the 32 MB and 256 MB deep memory options, the maximum sequencing specifications increase as well as the waveform memory. Deeper memory on traditional AWGs increases only the waveform memory and does not allow more sequence steps or waveform segments. Deep waveform memory can handle very long waveforms, but in some cases, deep waveform memory alone may not address very demanding applications. A complex sequence of segments defining a waveform can reduce the memory requirements of such applications.
For example, a video frame(s) contains many repetitive segments, such as vertical and horizontal sync pulses, the color burst, and blanking lines in the vertical blanking interval. With the SMC output data transfer core, a copy of each signal segment can be stored, and instructions (on linking and looping the sections) are stored in a sequence. In such an application, the large memory buffer may not be adequate for storing the entire image or multiple images, but can be accommodated by storing the key sections of the image and the sequence list specifying the generation of the frame(s). Such a sequence could easily consume more than the few kilobytes of SRAM instruction memory available in traditional AWGs. With the SMC architecture, the problem disappears with the large memory configurations where you can store the relevant segments of the frames(s) and the large sequence(s).
The SMC output engine optimizes test throughput because you can store multiple sequences, as shown in Table 5, thereby eliminating the setup time between tests. This feature, coupled with deep memory, can significantly increase test throughput because you can switch quickly from one sequence to another within a functional test that requires different test sequences. This capability is especially important for video testing where a set of industry-standard test patterns needs to be generated in rapid succession.