The NI LabVIEW High-Performance FPGA Developer's Guide

Publish Date: Oct 29, 2018 | 17 Ratings | 4.18 out of 5 | Print | 7 Customer Reviews | Submit your review


The LabVIEW High-Performance FPGA developer's guide summarizes the most effective techniques for optimizing throughput, latency, and FPGA resources when using the LabVIEW FPGA Module and NI FPGA hardware.

The PDF version of the guide is available from the Downloads side panel.

Table of Contents


  • Intended Audience
  • Prerequisites and References

High-Performance FPGA-Based Design

  • Advantages of FPGAs
  • High-Performance LabVIEW FPGA
  • Understanding the NI RIO Hardware Platform
  • NI RIO for PXI and the PC
  • NI RIO for Compact Embedded Applications
  • Selecting an FPGA Platform

High-Performance Programming With the Single-Cycle Timed Loop

  • The SCTL Versus Standard LabVIEW FPGA Code
  • Understanding the SCTL
  • Benefits of the SCTL
  • Restrictions of the SCTL

Throughput Optimization Techniques

  • Increasing the Clock Rate
  • Increasing the Number of Samples Processed per Call
  • Critical Path Reduction
  • Decreasing the Initiation Interval

Integrating High-Throughput IP

  • Recommended Sources of LabVIEW FPGA IP
  • LabVIEW FPGA High Throughput Function Palettes
  • IP Handshaking Protocols
  • Determining Processing Chain Throughput
  • The DSP48 Node
  • The Fast Fourier Transform
  • The Xilinx CORE Generator IP System
  • Integrating HDL IP
  • Integrating IP Into Software-Designed Instruments
  • Integrating IP From the Community

Timing Optimization Techniques

  • Determining and Specifying Latency With the SCTL
  • Reducing Latency Through Parallelization
  • Removing Pipelining Registers
  • Optimizing Data Types

Resource Optimization Techniques

  • FPGA Resource Types
  • Filling Up the FPGA
  • Optimizing Resources Through Data Types
  • Minimizing Front-Panel Controls and Indicators
  • Tweaking Output Overflow and Rounding Options
  • Initializing Feedback Nodes
  • Resource Balancing
  • Multiplexing Logic
  • Using the SCTL as a Way to Save Resources

Data Transfer Mechanisms

  • Throughput and Latency of Data Transfer Mechanisms
  • Transferring Data Within the FPGA
  • Transferring Data between the FPGA and the Host System
  • Transferring Data between Devices

Next Steps

  • Formal Training
  • Evaluating the NI RIO Platform
  • NI Alliance Partners and Services







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Customer Reviews
7 Reviews | Submit your review

any chance for an update?  - May 6, 2017

Great document! It is dated Feb 2014 and there are some new additions to LabVIEW FPGA since then.

error in Fig.61 on p.58  - May 4, 2016

Note the code example in Figure 61 on p. 58 of "labview_high-perf_fpga_v1.1.pdf (Revision No. 1.1 - Feb 2014) is incorrect. If the maximum element is either #5 or #6 out of the 8-element input array, it will not reach the "max" output node.

Good introduction but lacks technical detail  - Apr 2, 2015

I am using the SOM sbrio-9651 and so much of this does not apply to the 9651. Like there is the powerful DSP48 node on page 43 but is does not work on the 9651 and the introduction to the Xilinx core generator is good but it does not give enough information on actually using the core generator. I have a project I am trying to get done but productivity and performance have taken a hit because I don't have the information I need to get the maximum performance out of the 9651. Patrick LeBrun

Great reference  - Mar 18, 2014

Long overdue reference to squeezing the most our of FPGA designs. I'm currently doing a major (and I mean major) overhaul of our FPGA code and am employing designs I think are being viewed as being somewhat experimental (many SCTLs with VI-defined registers used as interface). I also initialise the registers within static LVOOP items.....

Wrong typing  - Mar 7, 2014

Last paragraph of page 76: - eed->need - Error! Reference source not found.

best resource yet for LV FPGA  - Feb 27, 2014

Very useful!

Publish if on track  - Sep 17, 2013

If its on track then why is it not published

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