PXI Digital Pattern Instruments Bring Semiconductor ATE-Class Digital to the Open PXI Platform

Publish Date: Aug 22, 2018 | 1 Ratings | 5.00 out of 5 | Print


PXI Digital Pattern Instruments delivers ATE-class digital to the industry-standard PXI platform for testing a broad range of RF and mixed-signal integrated circuits (ICs). The NI PXI platform and NI Semiconductor Test System (STS) are an ideal platform for characterization and production test of RF and mixed-signal ICs from RF front ends and power management ICs to transceivers and Internet of Things systems on chip with built-in connectivity and sensors.

Table of Contents

  1. Introduction
  2. PXI Digital Pattern Instruments
  3. NI STS Integration and Digital System Synchronization
  4. Digital Pattern Editor Software
  5. NI-Digital Pattern Driver
  6. TestStand Semiconductor Module
  7. Conclusion
  8. Next Steps

1. Introduction

PXI Digital Pattern Instruments combine the functionality of pin electronics hardware for digital interfacing and DC parametric measurements with digital timing flexibility by bursting digital patterns based on vectors with defined time sets and levels. Using various time sets allows for specifying different periods and edge placement from one vector to the next within a pattern. PXI Digital Pattern Instruments include many more features that give test engineers the ability to create complete test programs for their devices and device families.

The Digital Pattern Editor extends the hardware features of PXI Digital Pattern Instruments as a software tool for developing and editing files that comprise digital tests. The Digital Pattern Editor also adds powerful debugging features like History RAM tools, digital scope, real-time pin view, and system view, as well as a Shmoo tool for characterization and margining. The NI-Digital Pattern Driver is used to develop digital tests in LabVIEW, C, and .NET languages. The TestStand Semiconductor Module integrates test plan steps for all measurement types with results logging, database connectivity, part binning, and handler interfacing.


Figure 1. PXI Digital Pattern Instruments and the Digital Pattern Editor give semiconductor test engineers the features and tools they need in characterization and production.


The following sections detail each tool in NI’s solution for semiconductor digital test development and deployment.


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2. PXI Digital Pattern Instruments

PXI Digital Pattern Instruments burst vectors defined by time sets on a cycle-by-cycle execution model. These time sets can include different vector periods, edge placement, and drive formats.

Figure 2. The PXIe-6570 and PXIe-6571 digital pattern instruments are digital ATE modules in the PXI form factor; the PXIe-6571 can form digital subsystems with up to 512 synchronized pins.


The one-slot PXIe-6571 and two-slot PXIe-6570 are similar digital pattern instrument models that both use the Digital Pattern Editor and NI-Digital driver. See the table below for additional comparison.


Table 1. PXI Digital Pattern Instruments are built to perform characterization and production test of semiconductor devices.

PXIe-6570 PXIe-6571*

Module width

2 slots 1 slot

Active load

24 mA

16 mA

Pin electronics

Digital: -2 V to +6 V, 32 mA
PPMU measure voltage: -2 V to +6 V, 32 mA
PPMU force voltage: -2 V to +7V, 32 mA


32 per module

Vector rate

100 MHz (10 ns minimum vector period)

Data rate

200 Mbps

Clock generation rate

160 MHz**

Pattern timing

31 time sets
Edge placement resolution 39.0625 ps

Drive formats

Non-return (NR), return to low (RL), return to high (RH) (100 MHz max), surround by complement (SBC) (50 MHz max)

Vector memory depth

128 M/channel


Flow control, sequencer flags and registers, signal, source and capture, subroutine

Source and capture engines

Broadcast or site-unique
Serial or parallel
8 per instrument

Source and capture memory

256 Mbit source memory, 1 MSample capture memory

Frequency counters

5 kHz to 200 MHz, per pin

History RAM

(8,192/N sites) -1 cycles

SCAN support

Flattened SCAN patterns, up to 128 M

* Note that the PXIe-6571 requires a chassis with 82 W slot cooling capacity, such as the PXIe-1095. For more on PXI power and cooling, see this white paper.
**Clock rates > 133 MHz will have a non-50% duty cycle


Timing and Execution

PXI Digital Pattern Instruments burst digital data based on patterns that are made up of individual vectors. The time set includes the period of the vector in time, a drive format for the pin, and placement of the digital edges.

The drive formats, or vector formats, supported by these instruments are non-return, return to low, return to high, and surround by complement. Having the ability to use all of these formats gives engineers the ability to make the most efficient digital interface with as few vectors as necessary.


Figure 3. The combination of drive format and pattern value will determine what the digital waveform looks like.


The time sets for a PXI Digital Pattern Instrument have up to six drive edges and a compare strobe  to act on the formats defined above. Drive on and drive off are edges that determine when the pin drivers will enable and disable. Drive data and drive return define when the pin driver will assert a high or low level. The drive return edge is only used in return vector formats. The compare strobe specifies the time in a vector when the pin comparator determines if the pin is at a high, low, or midband voltage level based on defined thresholds.


Figure 4. Each time set for a PXI Digital Pattern Instrument has a defined period, up to six drive edges, and a compare strobe.


The placement of each of the edges above is limited by the edge placement resolution of the instrument, and each drive data and drive return edge must adhere to the minimum edge separation specification within a vector, and from one vector to the next. The PXIe-6570 and PXIe-6571 both have an edge placement resolution of just over 39 picoseconds.


Hardware Overview

PXI Digital Pattern Instruments have several types of vector and dynamic pattern memory and feature pin electronics. The block diagram in Figure 5 shows the instruments' functional hardware components.


Figure 5. PXI Digital Pattern Instruments offer advanced ATE memory features like history, source, and capture memory with the right levels of user abstraction.


Memory Features

Each channel or pin of a PXI Digital Pattern Instrument has access to vector memory. The PXIe-6570 and PXIe-6571 have a vector memory depth of 128 M/channel so that they can load many different patterns into memory and avoid downtime that comes from loading new patterns.

Source and capture memory are used to write dynamic data that is site-specific or determined only at run time, such as when an engineer needs to read or write registers or test analog-to-digital and digital-to-analog converters. PXI Digital Pattern Instruments have multiple source and capture engines per module to support reading and writing specific data to multiple sites. The PXIe-6570 and PXIe-6571, for instance, have eight source and eight capture engines with 1M samples of memory for each engine. Multiple source and capture engines empower a single digital pattern instrument to perform a calibration routine on multiple separate devices under test (DUTs) with different coefficients at the same time, while using the same pattern to write the register, all after calculating the register values from capture data on each device. The opcodes section below provides more detail on implementing source and capture memory.

When a pattern bursts, engineers can configure the History RAM to capture pattern results based on triggering conditions such as failures, cycle numbers, or vector labels. This can help to debug the pattern or perform failure analysis. Engineers can configure the History RAM, sometimes referred to as failure memory, to store a number of vectors or cycles of pattern execution data from the last pattern burst up to the limit of the PXI Digital Pattern Instrument in use. With the Digital Pattern Editor, engineers can configure the number of cycles the instrument stores in History RAM and the types of results. The History RAM overlay view of the Digital Pattern Editor provides a view of results on top of the expected pattern for debugging, flagging any failures in the pattern execution. The HRAM API can also be used for programmatic collection of failures.


Pin Electronics

Pin electronics provide the electrical interface to the DUT and allow the engineer to drive or receive digital data and emulate the conditions of other loads and components interacting with the device.

In a drive state, the pin driver of the pin electronics is engaged and forces the voltage on the pin to be low or high as determined by a 0 or 1 in the pattern. A pin driver will source or sink up to 32 mA to achieve the defined high or low value on the pin when enabled. Digital pattern instruments use 0 and 1 to represent drive pin states.

Compare states are non-drive states that use the comparators of the pin electronics to assess incoming data against predefined thresholds. Comparators are included in pin electronics and have settable levels for high and low voltages that are made in context to the DUT. To represent the different non-drive states that a pin can take, L, H, X, V, E, and M are all used.


Figure 6. Pin drivers and comparators within the pin electronics use defined voltage levels for drive and compare states in the digital pattern.


The termination mode specifies the electrical behavior of the pin when the pin function is set to digital and the pin state is not a drive state. PXI Digital Pattern Instruments support high impedance (also referred to as Hi-Z or tristate), active load, and VTERM.

Engineers can use high-impedance termination when they want their DUT to drive into a high-impedance load to reduce current flow. Active load termination, on the other hand, causes the digital instrument to source or sink current based on the commutating voltage and current limits set. This is advantageous when engineers want to emulate an active load connected to the DUT.  Finally, VTERM provides a 50 Ω termination to the VTERM voltage level. Setting VTERM to 0 V and selecting the VTERM termination mode has the effect of connecting a 50 Ω termination to ground for non-drive pin states. This can be useful for improving signal integrity of certain DUTs by providing 50 Ω termination while the DUTs are driving. Setting VTERM to a mid-level voltage and selecting the VTERM termination mode can be useful for DUTs that require an active termination.

PXI Digital Pattern Instruments also feature pin parametric measure units (PPMU) that source and sink voltage or current to make DC parametric measurements. The PPMU functions are commonly used for continuity or open/short and leakage testing. NI also has a large offering of source measure units (SMUs), which can be used when a higher voltage, current, or more precise measurement is required.


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3. NI STS Integration and Digital System Synchronization

PXI Digital Pattern Instruments make up the digital test subsystem of the STS. The instruments are supported in all STS software and are calibrated using a timing calibration load board and a DC calibration load board, both from NI. The diagnostic software and calibration tools ensure high reliability and uptime of the system. It also gives a single system the ability to have many unified digital test resources.


Figure 7. With PXI Digital Pattern Instruments, more test engineers can take advantage of the STS, a PXI-based, open platform semiconductor production test system.


PXI Digital Pattern Instruments can be synchronized together within a single PXI chassis using a PXI timing and synchronization module and the NI-Sync device driver. This synchronization can be done both within the STS and in a stand-alone PXI chassis. By synchronizing multiple instruments, a single digital subsystem can have up to 512 synchronized channels that achieve a specified edge placement accuracy performance. A unified digital subsystem can span single sites and combine match and failed conditions across multiple digital pattern instruments.


Figure 8. PXI Digital Pattern Instruments can be synchronized using a PXI Timing and Synchronization module to create a digital subsystem of up to 512 unified channels.


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4. Digital Pattern Editor Software

The Digital Pattern Editor is an interactive tool for importing, editing, or creating test patterns. The editor also includes tools like Shmoo plots to provide a deeper understanding of DUT performance across variation, as well as debug tools like overlaying pattern failures on a pattern or using digital scope to get an analog view of the pin data. The Digital Pattern Editor integrates editing sheets for device pin maps, specifications, and patterns to develop or edit imported digital test vectors and patterns. Features like multisite and multi-instrument pattern bursting empower the engineer to expand from development into production leveraging the same workflow. All of the sheets developed in the Digital Pattern Editor can be reused by the API in LabVIEW, C, or .NET languages, as well as in the TestStand Semiconductor Module.


Figure 9. The NI Digital Pattern Editor is a powerful digital test development, editing, and debugging tool.


Pin Map, Specifications, Timing, and Levels

The first tools an engineer uses when developing a test plan with the Digital Pattern Editor are the pin map editor and specifications sheet. The pin and channel map editor is used to view, create, modify, and save pin and channel map files, which define the relationships among pins, sites, channels, and instruments in the test system. All devices have, or need, specifications that define how it can be used. A test engineer can define these specifications and use them as variables in formulas throughout the Digital Pattern Editor.

Next, a test engineer defines the timing and levels of the digital interface with the device. This is where the vector components like drive formats and edge placement are defined, as well as the levels for the pin drivers and comparators. The timing document is used to view, create, modify, save, and apply timing files. Timing files include the vector period, data format, and edge placement information for pattern execution. Timing generally contains one timing sheet that can have many time sets. An engineer can create multiple timing files and apply those values to separate pattern bursts. The PXIe-6570 and PXIe-6571 can have up to 31 unique time sets for use within a pattern, providing flexibility in edge placement or frequency options.

The Levels Sheet is where the VOH, VOL, VIH, VIL pin driver, and comparator values are defined, as well as VTERM, VCOM, IOH, and IOL termination settings .


Figure 10. The Digital Pattern Editor window can be configured to view development sheets and debugging tools all at the same time.


Pattern Development and Format

The pattern file is a collection of vectors, with each vector containing time sets, labels, opcodes, pin states, and comments. The Digital Pattern Editor requires a compiled, binary version of the pattern file to edit or burst. Engineers can compile an ASCII text pattern file format (.digipatsrc) into a binary version using the Digital Pattern Editor or a command line process. The ASCII form can be used to convert existing patterns by following the well-defined pattern file format. Design simulation and SCAN files generated by EDA  tools can be cyclized and targeted to the NI format using existing customer in-house EDA workflows or third-party cyclizing tools. The Digital Pattern documentation can offer more information.

Having an open, defined ASCII pattern source format allows customers to generate their own patterns from EDA tools or convert patterns from other testers. ASCII pattern files can also be used to store revisions of the text pattern file in source code control systems, use a third-party application to compare revisions of the pattern file, or manually edit pattern files in a standard text editor.

Vectors in the pattern execute sequentially unless otherwise instructed using opcodes.



In many cases engineers can simplify their pattern, make it more reusable and robust, or match the data that the DUT is expecting by using opcodes. There are several kinds of opcodes that allow users to programmatically choose which vector, or when a vector, will execute. The Digital Pattern documentation can provide details for a specific opcode.


Flow Control

Several flow control opcodes determine the logical execution flow of the pattern and include branching operations, loops, and breaks.


Sequencer Flags and Registers

Engineers can use sequencer flags to coordinate execution between the pattern sequencer and a test program at run time. An example of using this opcode is setting a flag that can be read on the host computer to detect that the pattern has reached a certain point in its execution where a different measurement, such as the SMU reading the current flowing into the Vcc pin, can be made. This opcode shares handshaking software commands with the test program to take measurements and wait for events.



The set_signal, pulse_signal, and clear_signal opcodes define hardware events that can be routed to the PXI trigger lines to coordinate execution and can hold a specified state until the pattern executes the clear_signal opcode. This opcode enables routing events to PXI trigger lines to coordinate execution with other hardware systems or instrumentation. In this case, another PXI instrument could be triggered from a digital pattern instrument on the PXI backplane and share a handshake with the digital instrument very quickly to drive down test times.


Source and Capture

As discussed above, source and capture waveforms use the source and capture engines on PXI Digital Pattern Instruments to drive and collect dynamic data at run time. The same pattern file can be used for single or multisite source and capture operations.

The source and capture waveform configuration document in the Digital Pattern Editor and the NI-Digital Pattern Driver source and capture API can set configuration data for source and capture waveforms. Waveforms can also be loaded from .csv files. The waveform configuration document defines the waveform type, sample format and width, bit order, and pins or pin groups for the waveform. The programmatic creation of source waveforms can be done using the NI-Digital Pattern Driver API. For example, creating waveforms programmatically allows an engineer to generate a large number of possible register values to load to the digital pattern instrument at once.



The subroutine opcodes are analogous to procedure calls. The opcodes allow sections of the pattern to be branched to from other vectors in the pattern flow and then return back to the calling vector after executing all of the vectors in the subroutine.


Bursting the Pattern

Engineers can set a given pattern to burst on all enabled sites or only selected sites when burst in the Digital Pattern Editor or the NI-Digital Pattern Driver API. The Digital Pattern Editor also gives engineers the option to burst until fail, burst until pass, or burst until abort. With these burst options, engineers can see how robust the pattern is or if the DUT behaves as expected. When bursting a pattern from the Digital Pattern Editor, the execution always starts at the first vector of the pattern.


History RAM Overlay Feature and History RAM View

Engineers can view the History RAM in two ways: using the History RAM overlay feature in the pattern document and looking at the History RAM view.

With the History RAM overlay, the History RAM results are overlaid on the pattern. The overlay displays the subset of burst results that corresponds to vectors in the current pattern based on the settings specified in the History RAM and signal setup pane. The History RAM view includes the corresponding time sets, labels, opcodes, pattern names, vectors/cycles, pin data, and comments. Rebursting a pattern overwrites the data in the History RAM overlay mode and in the History RAM view.


Figure 11. History RAM is used to log the execution results of the last digital pattern burst and the Digital Pattern Editor will overlay these results onto the pattern for fast debugging.


In the History Ram overlay mode, vectors with a blue background display available History RAM results. Pin data cells with a red background and red text indicate a failure. Cell tooltips display expected and actual values for failures. For vectors that execute on more than only one cycle, the pattern document in History RAM overlay mode displays the superset of failures for all cycles with History RAM results.


Digital Scope

To aid engineers in debugging patterns, the digital scope tool displays a progressively updated two-dimensional plot of the actual analog levels of the digital waveform using the pattern, time set, and levels. The Digital Pattern Editor generates digital scope waveforms by repeatedly bursting a pattern while changing levels and the timing of the strobe edge to determine the level of the waveform at each point in time. Engineers can launch the digital scope plot by clicking the Show Digital Scope button on the pattern document toolbar or right-clicking a cell in the pattern document and selecting Digital Scope on Vector from the context menu.


Figure 12. The Digital Scope uses the edges of the time set to create an analog representation of the voltages each pin is driving or measuring.


Pin View

Engineers can use the pin view pane during debugging to interactively view and modify the current state of a single pin. The pin view provides access to the pin driver, active load, comparator, PPMU, and NI-DCPower instruments like power supplies and SMUs. The values that appear in the pin view pane are maintained from the previous burst of the pattern, even when first expanded. The pin view is a powerful tool to debug patterns by interactively changing specific values or observing pin behavior to identify unexpected behavior. Engineers can use the pin view in the Digital Pattern Editor to debug individual pins during the execution of code that uses the NI-Digital Pattern Driver at a breakpoint.


Figure 13. The pin view is a real-time soft front panel for individual pins in the instrumentation. The pin view can be used in conjunction with a breakpoint in your code to interactively debug pin behavior during execution.


System View

The system view displays the settings and measurements for all the pins in the active pin and channel map connected to a digital pattern instrument or to an NI-DCPower instrument. This full system view is a great way to monitor the status of instruments and channels in the system.


Figure 14. The system view is a real-time updating figure of all of the pins defined in the Digital Pattern Editor pin map. This view can be used to see status of pins during or after execution of a digital pattern burst or PPMU operation.


Shmoo Plot

The Shmoo tool displays a dynamically updated intensity plot of pass and fail values for a sweep of two variables. The Shmoo executes on multiple sites and engineers can switch the plot results displayed from site to site during the operation without hindering the sweep’s completion.

The Shmoo can sweep up to two variables including levels, voltages, currents, edges, or specifications at a time. The start, stop, and step size options determine the number of iterations the Shmoo operation executes. The Shmoo operation can execute in sweep, zigzag, progressive resolution, or edge traversal mode. For specifications variables, the Shmoo operation uses the values in the active levels file and the active timing file listed in the Project Explorer window. If a specification that is selected for one of the Shmoo variables is used in the timing or level sheets, those timing and levels vary based on the changing value of the specification.

Shmoo plots are critical for providing insights into the performance limits of a device over variation, which is important for device characterization.


Figure 15. A Shmoo plot displays the pass or fail outcomes of a digital pattern as two values in the project are swept with respect to one another.


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5. NI-Digital Pattern Driver

The next step in developing a full test program is automating tests with the NI-Digital Pattern Driver. Engineers can develop test code with the NI-Digital Pattern Driver in LabVIEW, C,  or .NET languages.

Interaction with a PXI Digital Pattern Instrument using the NI-Digital Pattern Driver uses a task handle that begins with initialization, followed by configuration, action, and close. Configuration steps include creating, editing, or loading a pin map, levels and timing, and patterns. Within the configuration operations, the engineer has the option to load the files generated by the Digital Pattern Editor. Actions in the NI-Digital Pattern Driver include bursting patterns, sourcing and measuring with PPMU functions, writing and reading source and capture memory, and setting flags. There are also utility and calibration functions that enable system diagnostics and synchronization. Using the API functions, engineers can create test programs that can dynamically generate, load, and burst patterns while interacting with other instruments in the test system.


Figure 16. The NI-Digital Pattern Driver API includes functions for initializing control, configuring, forcing actions, and closing control of the device. This API allows the user to create robust test sequences with all of the instrument functions available.


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6. TestStand Semiconductor Module

TestStand is an industry-standard test executive software that is used in many industries from production test of consumer electronics and large machines to semiconductor devices. Production semiconductor device test has specific requirements like part binning, STDF results logging, and user interface models that are added with the TestStand Semiconductor Module.

The TestStand Semiconductor Module works in conjunction with the Digital Pattern Editor and its outputs. Users of the TestStand Semiconductor Module with NI-Digital Pattern Driver and Digital Pattern Editor software can expect native pin map support, and the continued ability to enable multisite, DUT-centric programming of semiconductor test systems. That also goes for other files associated with Digital Pattern Editor projects, including specification files, pattern files, and level sheets that are linked to the TestStand Semiconductor Module through the Pin Map API. This allows for straightforward use of Digital Pattern Editor projects with the TestStand Semiconductor Module.

The Digital Pattern Editor can also be quickly accessed through toolbar navigation in the TestStand Semiconductor Module. A single click opens the Digital Pattern Editor, which gives users of the TestStand Semiconductor Module access to superior, native debugging features.


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7. Conclusion

PXI Digital Pattern Instruments are designed to test RF and mixed-signal ICs from RF front ends and PMICs to transceivers and IoT SoCs with built-in connectivity and sensors. These instruments deliver the performance, features, and tools necessary to test these semiconductor devices in both characterization and production. Designing a test system with instruments that can span from characterization to production is becoming necessary to create smarter test systems that scale with increasingly smarter devices, while meeting the shrinking time-to-market windows of the semiconductor industry.


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