1. LabVIEW FPGA Compile Cloud Service for NI Standard Service Program (SSP) Members
The LabVIEW FPGA Compile Cloud Service is now included in the LabVIEW FPGA Module for customers who have an active NI Standard Service Program (SSP) membership. The LabVIEW FPGA Compile Cloud Service gives you the ability to offload your LabVIEW FPGA compilations to high-performance, Linux-based servers in the cloud. It includes the following benefits:
- Offers up to 30% reduction in compile times for NI CompactRIO targets, and up to 60% reduction in compile times for NI FlexRIO and vector signal transceiver (VST) targets
- Provides the ability to execute multiple compilations in parallel
- Frees up development machine resources
- Provides the ability to shut down the development machine at any time during a compile
- Saves hard drive space if you choose to not install the Xilinx compilation tools locally (see the support document titled When Do I Need to Install the Xilinx Compilation Tools?)
In addition, the LabVIEW FPGA Compile Cloud Service requires zero on-site installation and maintenance. To start using this free service today, visit ni.com/trycompilecloud.
2. LabVIEW FPGA Compile Farm Toolkit
The LabVIEW FPGA Compile Farm Toolkit is now included in the LabVIEW FPGA Module. If you prefer to offload LabVIEW FPGA compilations to a farm of on-site workers versus sending them to the cloud, the LabVIEW FPGA Compile Farm Toolkit provides software to create an on-site server to manage FPGA compilations. You can connect as many worker computers as you need, and the central server software manages the farming out of parallel compilations and queuing. To reduce your FPGA compile times, the toolkit also includes support for Linux compile worker computers.
3. LabVIEW FPGA IP Builder
LabVIEW FPGA IP Builder is now included within the LabVIEW FPGA Module. LabVIEW FPGA IP Builder generates high-performance FPGA IP by combining high-level synthesis technology with the power of LabVIEW. You can use LabVIEW FPGA IP Builder to:
- Automatically optimize your LabVIEW FPGA VIs
- Easily port LabVIEW desktop code to the FPGA
- Quickly iterate with rapid performance and resource estimates
- Reuse your IP, unmodified, to adapt to different application requirements
For more information on LabVIEW FPGA IP Builder, see Using NI LabVIEW FPGA IP Builder to Optimize and Port VIs for Use on FPGAs.
4. LabVIEW FPGA IP Builder Improvements
The LabVIEW 2014 FPGA IP Builder includes new programming elements so you can create portable algorithms. New features include:
- Deferred Size Check for Arrays: Arrays can have variable sizes as long as the size can be determined at code generation. This makes it possible to create reusable subVIs that implement your algorithms. You can use the same subVI in different applications.
Figure 1. Arrays that are used in the IP Builder context can have variable sizes.
- Additional Tunnel Modes:
- Concatenating tunnels enable IP creation for processing multidimensional arrays. LabVIEW FPGA IP Builder (and LabVIEW FPGA) does not support multidimensional arrays. However, multidimensional arrays can be serialized and processed by your IP. Concatenating tunnels enable reassembling of multidimensional arrays.
- Conditional tunnels are useful for multirate algorithms like decimation, where the number of elements at the output is different from elements at the input.
Figure 2. Additional tunnel modes are supported within the IP Builder context in the LabVIEW 2014 FPGA Module.
- Conditional Disable Structure: This feature makes it possible to create portable algorithms that you can run on the desktop or in the IP Builder context.
Figure 3. The conditional disable structure can detect whether your code is executing in the Windows context or in the IP Builder context.
5. New Vision IP for LabVIEW FPGA
The NI Vision Development Module 2014 includes over 50 image-processing functions that can be offloaded to the FPGA for maximum processing performance, in addition to an API to pass images between the CPU and FPGA. For quick prototyping, you can use the Vision Assistant to automatically generate the LabVIEW Project and VIs for the FPGA, host CPU, and the interface between the two targets. You can modify the new vision IP through the LabVIEW FPGA IP Builder.
Figure 4. Offload new vision IP to FPGA hardware for maximum processing performance.
6. LabVIEW PID Toolkit
The LabVIEW PID Toolkit functionality for FPGA targets is now included in the LabVIEW FPGA Module. Use the LabVIEW PID Toolkit to implement single or multichannel proportional integral derivative (PID) control algorithms in LabVIEW FPGA. The included PID (FPGA) Express VI implements a fixed-point PID algorithm. A floating-point implementation of this same PID algorithm is included in the white paper titled Floating-Point Implementation of a LabVIEW FPGA PID Controller.
Figure 5. The latest version of LabVIEW FPGA includes a single or multichannel PID control algorithm.
7. Xilinx Vivado Support for Kintex-7 LabVIEW FPGA Targets
The new Kintex-7 FPGA and Zynq system on a chip (SoC) from Xilinx offer a perfect balance of FPGA fabric clock rate performance, low power, high-speed I/O, capacity, security, and reliability. In LabVIEW 2014, developers using Kintex-7 FPGAs or Zynq SoCs in their NI RIO hardware can also benefit from the latest compilation technology from Xilinx. The new Xilinx Vivado compilation tools offer several benefits including:
- More reliable, consistent timing closures
- Improved resource utilization
- Faster compiles for Kintex-7 FPGA and Zynq SoC targets previously using Xilinx ISE (NI cRIO-9068 and NI PXIe-7975R)
Figure 6. Xilinx Vivado offers reduced compilation times for Kintex-7 and Zynq SoC targets
For a list of all NI RIO hardware that uses Kintex-7 FPGAs, see the support article titled Which Xilinx FPGA Chips Are Used by National Instruments RIO Devices?
8. 4-Wire Handshaking API for FIFOs
Four-wire handshaking is commonly used in high-throughput streaming applications. First-in-first-out memory buffers (FIFOs) are commonly used to transport data between processing elements within these applications. The new 4-wire handshake interface on FIFOs gives you the ability to easily integrate them in high-throughput designs.
Figure 7. Use a 4-Wire Handshaking API for FIFOs that you can easily integrate into high-throughput streaming applications.
9. Higher Performance BRAM
Xilinx Block RAM has optional registers at the output. By enabling these registers, you can effectively pipeline the memory and break up the critical path, and synthesize their design at a higher clock rate. It is important to note that enabling the registers adds latency to the memory access, and you need to add feedback nodes equal to or greater than the cycles of latency configured.
Figure 8. Take advantage of high-performance BRAM to synthesize your design at a higher clock rate.