LabVIEW FPGA 2013 Productivity Enhancements and Optimizations

Publish Date: May 30, 2014 | 7 Ratings | 5.00 out of 5 |  PDF

Overview

The NI LabVIEW FPGA Module helps embedded designers use less engineering resources and finish projects faster than with other FPGA design tools. Added improvements in LabVIEW FPGA 2013 help you create advanced embedded and test systems in less time with the latest technologies. The module offers powerful new features for shortening your development time and improving the performance of your application. See the following highlights of some of the top new features.

Table of Contents

  1. Productivity Enhancements
  2. Proficiency Resources for LabVIEW RIO Developers
  3. Compatibility With the Latest Hardware
  4. Next Steps
  5. Reference

1. Productivity Enhancements

 

FPGA High-Performance Linear Algebra Library

Advanced applications such as radio frequency communications, image and audio processing, heat distribution, and cryptography require high-performance algorithms on reconfigurable hardware. LabVIEW FPGA 2013 includes new IP libraries that allow you to easily implement FPGA-based high-performance algorithms.

Building basic linear algebra operations with specific timing, resource utilization, and throughput requirements in FPGAs can be a challenging task. LabVIEW FPGA 2013 alleviates this challenge by introducing a new IP library including the most common linear algebra functions: matrix transpose, dot product, vector norm square, and matrix multiply.

 

Figure 1. LabVIEW FPGA 2013 includes a new IP library featuring the most common linear algebra operations.

 

These operations serve as basic building blocks for many numerical linear algebra applications, including the solution of linear systems of equations, linear least square problems, eigenvalue problems, and singular value problems. 

 

 

Figure 2. The LabVIEW FPGA 2013 linear algebra library helps you meet your requirements on timing, resources, and throughput.

 

Instrument Driver FPGA Extensions

Test engineers now have even more options for programming their software-designed instruments such as NI vector signal transceivers (VSTs) with the release of instrument driver FPGA extensions. This feature combines the compatibility of the full-featured NI-RFSA and NI-RFSG instrument drivers with the flexibility of the completely open source LabVIEW sample projects and instrument design libraries. You can add application-specific IP to your VST FPGA while preserving all of the features of the NI-RFSA and NI-RFSG instrument drivers, and without modifying those APIs. Potential FPGA enhancements include custom and/or novel instrument capabilities such as frequency mask triggering, better system integration through hardware-timed device under test (DUT) control and the deterministic triggering of other instruments, accelerated test throughput with FPGA-based measurement acceleration and coprocessing, and even closed-loop or “protocol-aware” tests in which the instrumentation hardware responds to the DUT in real time.

 

Figure 3. Instrument driver FPGA extensions give you the ability to define custom capabilities for software-designed instruments, while preserving instrument driver functionality and APIs.

 

 

 Improved Verification Tools for FPGA VIs With Simulation

It is critical to simulate FPGA designs because it ensures the correct functionality of algorithms before going through the compilation process, which can take minutes to hours. In LabVIEW FPGA, you can verify your algorithms through simulated I/O and traditional debugging techniques by simulating FPGA VIs on the development computer. LabVIEW FPGA 2013 delivers additional features and enhancements to this area.

 

Improved Signal Visualization in Debugging Tools

You can use traditional debugging tools such as probes, execution highlighting, breakpoints, and single-stepping when simulating your FPGA VIs on the development computer. However, in FPGA designs that involve communication protocols, you need to view signals in relation to each other with history data in order to debug the application. LabVIEW FPGA 2013 introduces a new probe based on sampling events that makes it easy to visualize signals on a waveform graph including relevant timing information.

Figure 4. The Sampling Waveform Probe allows you to easily visualize multiple signals on a waveform graph based on sampling events.

 

The Sampling Waveform Probe can use While Loops, For Loops, and FPGA clock domains as sampling event sources. Multiple wires on the block diagram can be associated to those sampling sources so they can be visualized altogether on the Sampling Probe Watch Window. This new way of visualization makes it easier to analyze multiple signals, especially when they are generated within a single-cycle Timed Loop.

 

Extended I/O Simulation and Timing Control Capabilities

LabVIEW FPGA gives you the ability to generate I/O signals to simulate the functionality of real-world I/O. This is traditionally done by simulating random data or configuring a custom simulation VI. LabVIEW FPGA 2013 offers a more direct path for providing simulated data to your LabVIEW FPGA VI.

 

Figure 5. The FPGA Desktop Execution Node facilitates the simulation of FPGA VIs in the development environment.

 

The FPGA Desktop Execution Node in LabVIEW FPGA 2013 facilitates the simulation of individual FPGA VIs on the development computer. Based on a configuration dialog, it allows the selection of the appropriate I/O terminals as well as the FPGA clock to be used during the simulation within While Loops, and interaction with models inside of simulation loops using the LabVIEW Control Design and Simulation Module. These simulations have increased timing fidelity with respect to primitives, dynamics of DMA FIFOs, and single-cycle Timed Loops.

 

Figure 6. The FPGA Desktop Execution Node is a configuration-based simulation harness that provides direct access to I/O terminals and timing resources of the FPGA.

 

 

Dynamic Bitfile Deployment Options

Bitfiles contain all the information required to configure an FPGA device and are the result of the compilation process. The reconfigurable nature of FPGAs resides in these files in such a way that you can modify the functionality of a deployed device on the field by downloading a new bitfile dynamically. LabVIEW FPGA 2013 includes new options to manage and deploy different personalities for FPGA targets.

 

Dynamically Loading Multiple FPGA Interfaces

Dynamically specifying a bitfile at run time gives you the ability to create field upgradeable FPGA-based applications. Traditionally, LabVIEW FPGA users had to use multiple static references using the Open FPGA VI Reference node to share an FPGA interface with multiple bitfiles.

Figure 7. Before LabVIEW FPGA 2013, users had to specify static references to manipulate multiple bitfiles.

 

In LabVIEW FPGA 2013, you can use the new Open Dynamic Bitfile Reference function to select multiple bitfiles at run time through a given path input. With this function, multiple bitfiles can use a common FPGA interface as long as they share the same named set of controls, indicators, and DMA FIFOs. You can use this function to create more flexible host interfaces for advanced applications. 

 

Figure 8. LabVIEW FPGA 2013 allows the sharing of a single FPGA interface with multiple bitfiles specified at run time by a path input.

 

Web-Based Bitfile Deployment

New in 2013, you can update the FPGA bitfile on next-generation NI CompactRIO devices through the Web-Based Configuration and Monitoring interface. This process only requires a Silverlight-enabled web browser and an FPGA bitfile, and makes it easier to manage the embedded target’s configuration.

Figure 9. Bitfiles for FPGA chips in CompactRIO targets can now be updated through the Web-Based Configuration and Monitoring interface.

 

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2. Proficiency Resources for LabVIEW RIO Developers

In addition to performance improvements, LabVIEW FPGA 2013 is accompanied by a series of resources to complement your training and guide you through programming LabVIEW reconfigurable I/O (RIO) hardware with recommended architectures and development practices.

 

High-Performance RIO Developer's Guide

Similar to the popular NI LabVIEW for CompactRIO Developer's Guide, the High-Performance RIO Developer’s Guide helps you understand and apply high-performance RIO concepts such as single-cycle Timed Loop programming, data streaming, pipelining, handshaking, VHDL code integration, and other performance optimization techniques using NI FlexRIO and the NI PXI platform.

Figure 10. The High-Performance RIO Developer’s Guide instructs you on best practices and recommended architectures for advanced FPGA-based applications.

Self-Paced Online Training for LabVIEW Real-Time and FPGA

If you don’t have the time or resources to participate in an instructor-led training program, LabVIEW Real-Time 1, LabVIEW Real-Time 2: Architecting Embedded Systems, and LabVIEW FPGA are now available as self-paced online training. NI self-paced online training is a cost-effective alternative that is accessible 24 hours a day from ni.com/self-paced-training with your ni.com user profile information. Use self-paced online training for a quick refresher on technical topics or to prepare for an upcoming certification exam. 

Figure 11. NI self-paced online training now offers new options such as the LabVIEW Real-Time and LabVIEW FPGA online courses.

 

Certified LabVIEW Embedded Systems Developer (CLED) Certification

You can now design control and monitoring systems with confidence by obtaining the Certified LabVIEW Embedded Systems Developer (CLED) certification. A CLED demonstrates proficiency and expertise in analyzing requirements and designing, developing, debugging, and deploying mission critical, medium- to large-scale control and monitoring applications. To learn more about this certification, see ni.com/CLED.

Figure 12. The CLED certification completes the spectrum of obtainable LabVIEW qualifications by embedded programmers.

 

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3. Compatibility With the Latest Hardware

In addition to the new features and enhancements in LabVIEW FPGA 2013, you now have access to the latest FPGA targets that deliver increased processing power and performance.

 

Extended Processing and Throughput Capabilities With the NI cRIO-9068 System

As part of the LabVIEW RIO architecture, the new NI cRIO-9068 software-designed controller is based on the Xilinx Zynq-7020 all-programmable system on a chip (SoC). This chip features a 667 MHz dual-core ARM Cortex-A9 processor along with the Artix-7 FPGA with 85k logic cells and 220 digital signal processing (DSP) slices under the same enclosure. These two processing elements are communicated using an AXI bus with 16 DMA channels and 300 MB/s throughput. The cRIO-9068 controller offers high performance with low-power consumption for advanced control and monitoring applications powered by LabVIEW FPGA.

Figure 13. The cRIO-9068 system features the Xilinx Zynq-7020 all-programmable SoC for additional processing and throughput capabilities.

 

Increased Performance With 7 Series FPGA Family

The newest NI FlexRIO FPGA module combines the impressive signal-processing power of the 7 Series family with flexible, customizable I/O to form a high-performance, reconfigurable instrument powered by LabVIEW FPGA. The new NI PXIe-7975R is capable of streaming data at rates of up to 1.6 GB/s through its PCIe backend, and at up to 10GB/s to its 2 GB of on-board DRAM, enabling data-intensive applications such as medical imaging and record and playback. The available internal memory and digital-signal processing (DSP) slices make it ideal for real-time processing and analysis in RF communications and scientific research.

 

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4. Next Steps

View a Complete List of New Features in LabVIEW 2013

Check Out Evaluation Options for the LabVIEW RIO Architecture

Purchase the LabVIEW FPGA Module Now

See an Overview of LabVIEW FPGA Hardware Targets

 

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5. Reference

See Features in Past Versions of the LabVIEW FPGA Module

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