Design and Deploy FPGA-Based Controllers

Publish Date: Jul 29, 2010 | 3 Ratings | 5.00 out of 5 | Print

Overview

Although high-volume commercial applications engineers have widely adopted field-programmable gate arrays (FPGAs), other areas, such as industrial control and simulation, have seen a slower adoption rate. FPGA-based systems provide attractive features, such as inherent flexibility, high-speed performance, parallelism, and low-level reconfigurability. Industrial control design and simulation vendors are creating the next-generation FPGA development toolchains for engineers with little or no digital design expertise.

Table of Contents

  1.  Flexible, High-Performance Targets
  2.   FPGA Controller Design and Implementation
  3.  Autopilot Controller Case Study
  4.  Motion Controller Case Study
  5. Motion Controllers And Observer Structures Case Study
  6. One Tool for Design and Implementation

1.  Flexible, High-Performance Targets

Recent benchmark reports suggest that some FPGAs may have bypassed processors and digital signal processors with respect to cost and power consumption per signal processing unit. You can use NI LabVIEW to transition your control system implementation from a traditional processor-based target to an FPGA-based target.

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2.   FPGA Controller Design and Implementation

The following design-by-emulation example replaces a properly designed continuous-time (CT) controller with a discrete-time (DT) equivalent, which emulates the CT design. There are three stages to FPGA control design and implementation:

 

1. CT controller design, simulation, and implementation – In this stage, design the controller to comply with specifications such as rise time, maximum peak overshoot, settling time, and steady-state error. Then, simulate the controller in the closed-loop with the CT plant. Finally, implement the CT analog controller.

 

2. Floating-point digital controller implementation – In this stage, take the properly designed CT controller from the previous stage and discretize it based on the discretization period at which the digital system will run. Consequently, simulate the DT controller in the closed-loop along with the CT plant. Such simulation shows whether the resulting closed-loop system is stable and specifications are still met with the equivalent DT controller. If the closed-loop system is unstable, or specifications are not met, rediscretize the controller by changing the discretization method, or increasing or decreasing the sampling period.

 

3. Fixed-point digital controller implementation – In this stage, take the properly discretized DT controller from the previous stage and convert it to fixed-point (FXP). Note that the sampling period in the previous stage is the period at which the FPGA system will run. Consequently, simulate the resulting FXP controller in the closed-loop along with the CT plant. Such simulation shows whether the resulting closed-loop system is stable and specifications are still met with the equivalent FXP DT controller. If the closed-loop system is unstable, either the sampling frequency is too high or the FXP representation is truncating word length. 

Figure 1. FPGA Design Flowchart

 

Figure 2 shows the design cycle. Ideally, the system responses y(t), y'(t), and y''(t) are as close as possible. 

 

Figure 2. Design Stage Simulation

 

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3.  Autopilot Controller Case Study

This case study is inspired by the book Feedback Control of Dynamic Systems, in which engineers design a Piper Dakota airplane autopilot, as shown in Figure 3.  The specification is to have the system respond to a step in the elevator input with a rise time of less than 1 s and an overshoot of less than 10 percent.

Figure 3. Autopilot Case Study

 

Figure 4 shows a front panel associated with the plant TF [G(s)] and a properly designed controller TF [Gc(s)]. 

Figure 4. Autopilot Control Design and Discretization

 

The plots below show the three system responses from the previous section, where the controller Gc(s) was sampled at a period of 0.1 seconds. Note that, while in this particular case the CT controller was properly designed and met all specifications, such sampling time is not fast enough and results in an unstable closed-loop system.

Figure 5. Autopilot Step Responses with a 0.1 s Sampling Rate

 

By decreasing the sampling time to 0.01 s, the closed-loop system becomes stable and the three responses almost match, as shown in Figure 6. Note that the error signal between the FP DT implementation and the FXP DT implementation is of the order of the resolution guaranteed by the FXP radix that was specified for the FXP TF.

 

Figure 6. Autopilot Step Responses with a 0.01 s Sampling Rate

 

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4.  Motion Controller Case Study

This case study is inspired by the book Observers in Control Systems: A Practical Guide, in which an engineer designs a motor position controller. The reference signal to track is a 2 Hz square wave with ±1 amplitude. The controller Gc(s) is a Proportional-Integrator (PI) controller with gains Ki=30 and Kp=1.5. The amplifier Ga(s) is a power converter modeled as a two-pole lowpass filter (LPF) with a bandwidth of 50 Hz and a damping ratio, ζ, of 0.707. The plant Gp(s) is modeled as an integrator with proper scaling. The sensor Gs(s) is modeled as a single-pole LPF with a bandwidth of 20 Hz. Figure 7 shows the block diagram.

 

Figure 7. Motion Controller Schematic

 

Figure 8 shows the corresponding LabVIEW block diagram.

 

 

Figure 8. Motion Control Design and FPGA Implementation Block Diagram

The plots in Figure 94 show the system responses from the first example, where the CT controller Gc(s) was sampled at a period of 0.01 s. Note that, while in this particular case the CT controller was properly designed and met all specifications, such sampling time is not fast enough and results in an unstable closed-loop system.

 

 

Figure 9. Autopilot Responses with a 0.01 s Sampling Rate


By decreasing the sampling time to 0.001 s (1 kHz), the closed-loop system becomes stable and the three responses almost match. Note that the error signal between the FP DT implementation and the FXP DT implementation is of the order of the resolution guaranteed by the FXP radix that was specified for the FXP TF.

 

 

 Figure 10. Motion Control Responses with a 0.001 s Sampling Rate

 

  

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5. Motion Controllers And Observer Structures Case Study

This case study is inspired by the book Observers in Control Systems: A Practical Guide, in which an engineer improves motor position controller loop performance by including a control loop observer. Observers are algorithms that use control system component models and system signal knowledge to produce system state estimates. For motion control, an observer can produce feedback signals superior to sensor output alone. To understand how observers can improve control system performance, consider the prototypical block diagram shown in Figure 11.

 

Figure 11. Generic Motion Controller Schematic

 

 

Ideally, the feedback control loop should use the true system output, or the signal immediately following the plant Gp(s). However, that signal is inaccessible. The only one available is the signal coming out of the sensor Gs(s). Control system design often ignores sensor transfer function, or Gs(s).

 

Some sensors or their built-in filters can cause phase lag, attenuation, and noise. Phase lag reduces loop stability margins. Electromagnetic interference generates noise, corrupts output, and wastes power. To solve this problem, you can run a plant model parallel to the process and use the output for feedback. However, the model is only an estimate of the real plant. Consequently, the signal coming out of the plant is an estimate of true plant output.

 

Compare the true system output with the estimated system output. The resulting error signal inputs into a compensator block, Gco(s), that eliminates all error. This is an observer.

 

Figure 12. Generic Motion Controller Schematic with Observer

Next, implement the observer structure to improve motion control loop performance from the second case study. The observer compensator block is a Proportional-Integral-Derivative (PID )control block with the following transfer function:



Figure 13 shows system response both with and without an observer. Note response improvement when there is an observer in the control loop.

 

 

 Figure 13. Motion Control Responses with Observers

 

Next, discretize the observer blocks with a 0.01 ms sampling period. The response is fairly close to that obtained with the CT observer, as Figure 14 shows. To implement the DT observer, run it at a very high loop rate of 0.1 MHz. FPGA targets are ideal to run observer blocks due to their capacity to run algorithms at high speeds.

 

Figure 14. Motion Control Responses with Observers

 

 

Finally, having successfully designed the DT observer, convert it to FXP. The plots below illustrate the closed-loop control system response with the CT observer, FP DT observer, and FXP DT observer.

 

Figure 15. Motion Control Responses with Observers

 

 

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6. One Tool for Design and Implementation

Today, it is easier than ever to close the gap between continuous-time controller design and FPGA implementation. LabVIEW, the LabVIEW Control Design and Simulation Module, and the LabVIEW FPGA Module make it simple to quickly perform control design, discretization, and implementation with a single toolchain. And adding observers can help improve control system performance.

 

Learn more about the LabVIEW Control Design and Simulation Module.

 

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Bibliography

Franklin, Gene F., J. David Powell, and Abbas Emami-Naeini. 2002. Feedback Control of Dynamic Systems: Fourth Edition. Prentice Hall.

Ellis, George. 2002. Observers in Control Systems: A Practical Guide. Elsevier.

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