1. FPGAs Are Getting More Difficult (Not Easier) to Compile
The FPGA compiler is not one big monolithic algorithm. Instead, it is a collection of large, complex algorithms. The computational challenge is taking your design through a flow that generates an optimized layout on a chip with millions of processing elements that you can configure in any way. The compiler uses synthesis to create a system of logical connections between processing elements. The compiler then maps, places, and routes in an iterative process to find the best solution and hook everything up on the physical chip while attempting to stay within user constraints. As you can imagine, the mathematics behind finding a globally optimized solution to a problem that has infinite possibilities is nontrivial. Hence, FPGA compilation can take hours (or longer with higher density silicon).
To improve compilation time, you can offload your compile to a separate, high-end, dedicated Windows machine with lots of RAM and a good processor. And to even further reduce compile time, you can install the compile tools on a Linux system to take advantage of compile tool performance optimization. NI has architected the LabVIEW FPGA compile system to make it easy to set up either of these options within your own company, or even target your compilations to zero-maintenance, high-end computers in the cloud.
2. LabVIEW FPGA Compile System Overview
NI has architected the LabVIEW FPGA compile system with three fundamental software components, resulting in a modular, scalable compile solution. The compile system is split into three parts: the development computer, the server, and any number of workers.
LabVIEW FPGA Module Development Environment —The LabVIEW development environment that you are familiar with is where you create your application. Once you press the Run button on your FPGA VI, it completes the Generating Intermediate Files step (see LabVIEW FPGA Compilation Process for more information). After generation, the development computer sends the intermediate files through web services communication to the FPGA compile server.
FPGA Compile Server—The server accepts compile jobs from one or many LabVIEW FPGA development systems and looks for available workers to farm out the compilation job. If no workers are available, the server holds the compile job in a queue until a worker becomes available.
FPGA Compile Worker—The worker has the Xilinx compilation tools installed on it for FPGA design synthesis, mapping, placing, and routing. With these tools, a worker executes the compile on the design and eventually generates a bit file that it sends back to the server, where the server sends it back to the development computer.
Figure 1. The LabVIEW FPGA compile system architecture includes three parts: the development computer, the compile server, and the compile worker(s).
The benefit of this compile system architecture is that it supports multiple workers and the automatic farming of compilation jobs. The server handles the queuing and farming, and is fault-tolerant to workers dropping in and out. In fact, if a worker drops out during a compilation job, the server can detect it and farm the compilation to another available worker. Although the compile job has to start over, it finishes without any action on your part. Because the communication lines between the development environment and the LabVIEW FPGA compile server are all robust web services, the compile system is fault-tolerant to a number of development-side issues as well, like a development computer restart.
3. LabVIEW FPGA Compile System Out-of-Box Options
Out-of-the-box the LabVIEW FPGA Module includes two compile system options. You can compile directly on your development machine or transfer the compile to a single, remote, dedicated compile machine.
By default, one server and one worker are installed on the development computer with LabVIEW FPGA. If you have used LabVIEW FPGA Version 2009 or earlier, this setup behaves in exactly the same way, with the compilation implementing on the development computer. To the compile server, it is as though the compilation were on a separate computer called “localhost” because the system is designed from the ground up to support distributed compilation.
Figure 2. By default, LabVIEW FPGA installs both the compile server and compile worker on the development computer and executes the compile using the development computer’s resources.
If you want to set up a more sophisticated compile system structure, you can install the server and a worker on another computer. To set up the remote compile server, you install just the compile tools from the LabVIEW Platform DVD. For step-by-step instructions on this process, refer to the Installing and Activating the LabVIEW FPGA Compile Server on a Remote Computer KnowledgeBase article.
Figure 3. LabVIEW FPGA supports a simple, single-machine, offloaded compile server without any add-ons.
Once the remote computer is set up with the compile tools, you can point the development machine to this new compile server by selecting Connect to a network compile server when you press the Run button. Alternatively, you can set this compile option from the Tools»Options»FPGA Module page.
Figure 4. Target the remote FPGA compile machine by selecting the compile system option and specifying where the server resides.
4. Offload FPGA Compilation
FPGA compilation grows computationally more complex and, thus, longer, as engineers use more sophisticated FPGA technology. To conserve resources on your development machine, the LabVIEW FPGA compile system architecture includes options to offload the compilation to dedicated computers. These should be high-end computers with good processors and high levels of RAM. Table 1 shows the minimum RAM needs for various Xilinx Virtex-5 FPGAs.
Table 1. Follow these recommended RAM guidelines for Xilinx Virtex-5 and Zynq-700 FPGAs. (Source: Xilinx Memory Recommendations Using the ISE Design Suite)
Performance for a compilation job is most negatively impacted when the process is starved for system memory and has to page on the hard drive or, in some cases, quit. Follow the recommendations in Table 1 for the best results. For a 32-bit server, you should have 4 GB of RAM and only compilation tools installed. You can use the 3 GB Windows switch to maximize the amount of RAM the OS can allocate to the compilation. As you can see from the chart, 64-bit systems should have more RAM installed. Of course, those systems can address much more than 4 GB of RAM, so, in that case, the more the better—up to 16 GB.
Offload to a Single Computer
As mentioned, you can use LabVIEW FPGA to install the server and worker on a separate computer and target compilation. To do this, follow the steps in the Installing and Activating the LabVIEW FPGA Compile Server on a Remote Computer KnowledgeBase article.
Figure 5. A simple, single-machine, offloaded compile server is supported by LabVIEW FPGA without any add-ons.
Offload to a Compile Farm
With the LabVIEW FPGA Compile Farm Toolkit, you can create an in-house compile farm that has many workers and can be targeted by multiple developers. The pricing for this toolkit is tiered according to the number of computers you need in the farm. With this toolkit, any number of developers can target the central server. The server is responsible for farming out the compilation jobs to all available workers. Because you have multiple workers, the compiles run in parallel. If there are no available compile workers, the server queues the requests (FIFO) and farms them out when a worker becomes available.
Figure 6. On-Site Compile Farm Architecture With One Server and Multiple Workers
Offload to an Online Compile Cloud Server
The final FPGA compile option uses the compile servers and compile workers that NI has made available online in the cloud. For ease of use, NI has added hooks directly from LabVIEW FPGA to enter a login, and with zero additional installation, you can offload your compiles to the cloud. Because the LabVIEW FPGA Compile Cloud Service is running the compile tools on Linux with the latest dedicated high-RAM high-end computers, you can see a substantial reduction immediately in the time it takes to compile your FPGA VI, compared to a standard Windows desktop computer. Compiling in the cloud also adds the capability to compile many VIs in parallel.
To target the cloud service, use the normal dialog box for the LabVIEW FPGA compile server, except select the online cloud service, and enter your user name and password.
Figure 7. Connect to the cloud through LabVIEW to reduce compile time and offload compilations.
Once you have this set up, the service compiles to the cloud rather than your local computer or local farm. The connection uses the latest IT industry security measures, which are similar to those used by other Internet services, such as banking.
>> Learn more or purchase the LabVIEW FPGA Compile Cloud Service.
Figure 8. Cloud Architecture for Offloading Compilations
5. Reduce Compile Time With Linux
NI has invested in supporting the FPGA compile worker on the Linux OS. Depending on your FPGA VI complexity and logic, you can expect the Linux compile worker to reduce compile times by approximately 20 to 50 percent, compared to a Windows compile worker. Xilinx originally designed and optimized the compile tools for the Linux OS, which explains this substantial reduction in compile time.
Figure 9. LabVIEW 2012 FPGA and later support FPGA compile tool installation on Linux machines, resulting in reduced compile times.
6. Next Steps
The LabVIEW FPGA compile system provides flexibility through the compile server and worker architecture to offload the processor intensive FPGA compilation process from your LabVIEW development computer. It also reduces compile times by using a compile worker based on Linux. Once you have selected the FPGA compile option that is appropriate for your team, follow the links below to learn more on how to set it up.
Set up a compile worker based on Linux.