LabVIEW NXG 4.0 FPGA Module Bug Fixes

Publish Date: Oct 30, 2019 | 0 Ratings | 0.00 out of 5 | Print

Overview

The following items are a subset of known issues fixed between LabVIEW NXG 3.1 FPGA Module and LabVIEW NXG 4.0 FPGA Module. If you have a Bug ID, you can search this list to validate that the issue has been fixed. This is not an exhaustive list of all bugs fixed in this release and does not capture bugs that were fixed in LabVIEW NXG.

ID

Fixed Issue
572838 Reported Compile Duration may be incorrect after reconnecting to compilation
718663 A generic back-end compile error is thrown when compiling designs with DMA FIFOs or DRAM in clock domains of 500 MHz or greater. The case is not supported and a more descriptive error message has been added.
727385 I/O Constants are incorrectly renamed when a FAM associated with that I/O is removed and then re-added.
704962 Memory resources configured for LUT storage display a read latency of 1 cycle in the disabled drop-down configuration menu when the actual read latency is 0 cycles.

 

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