Archived: LabVIEW 2011 and 2011 SP1 FPGA Module Known Issues

Publish Date: Jul 22, 2018 | 1 Ratings | 3.00 out of 5 | Print

Overview

This document has been archived and is no longer updated by National Instruments.

This document contains the LabVIEW 2011 FPGA Module known issues that were discovered before and since the release of LabVIEW 2011 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

The LabVIEW 2011 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.

Table of Contents

Document Organization

The Known Issues Document is divided into two separate tables. The following section displays the issues by issue category.

Known Issues by Category

Please refer to Developer Zone Article LabVIEW Known Issues Categories Defined for an explanation of the categories and what types of issues are in each category.

For those who wish to locate the newly reported issues, we have also have published a section of the known issues table sorted by the date the issue was added to the document.

Known Issues by Date

Contacting NI

Feel free to contact NI regarding this document or issues in the document. If you are contacting NI in regards to a specific issue, be sure to reference the ID number given in the document to the NI representative. The ID number contains the current issue ID number as well as the legacy ID number (use the current ID number when contacting National Instruments). You can contact us through any of the normal support channels including phone, email, or the discussion forums. Visit the NI Website to contact us. Also consider contacting us if you find a workaround for an issue that is not listed in the document so that we can add the workaround to the document.

Known Issues by Category

The following items are known issues in LabVIEW 2010 and 2010SP1 FPGA Module sorted by Category.

Building and Distributing LabVIEW Applications
171971 TCP must be installed
93395 4GIHITXE Modifying conditional disable symbols requires recompile
95971 Error compiling empty external clock loop
308548 The Xilinx map program can crash if a file named "map" can be found anywhere on your system path.
247993 Removing a C-Series Module in a Project Forces Recompilation
354689 Customer designs may fail with an over-mapping error if Output data and enable are synchronous to different clocks
313960 DSP48s Are Not Properly Optimized with Integer Constants in LabVIEW FPGA 2011
Compatibility
156070 Save for Previous of FPGA IO Nodes from 2009 and later to 8.6 and earlier can cause broken run arrow.
288024 VI-defined memory loses initial values after Save for Previous for 8.6 and earlier.
Controls and Indicators
307714 Silver controls are not available on Controls palette in FPGA VI context.
External Code
238241 When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.
283397 All CLIP vhd files must have a lowercase vhd extension.
303501 Xilinx compile errors occur when using the IP Integration Node to integrate VHDL with string constants defined in package files in the generic and/or port declaration.
304569 The post-synthesis model of a ngc file will fail to simulate if the file name of the ngc file is different from the ngc component name.
297138 The length of the port name in the top-level VHDL file of a CLIP should not exceed 22 letters.
300339 Estimated Device Utilization Incorrect or Not Available for Certain Projects and Targets
357304 LabVIEW FPGA Derived Clocks Do Not Behave Properly Within FlexRIO Adapter Module CLIP
Functions, VIs, and Express VIs
150867 "Not supported for current target" message may occur when Preallocate Arrays is not set.
151047 High-Throughput Math Library node fails to compile if pipeline stage exceeds 64
217824 FIFOs with built-in control are not supported with cycle-accurate simulation.
232504 Compilation on Spartan-6 FPGAs fails when compound add is placed before Loop Condition terminal.
296185 Interleaving two arrays with different fixed-point configurations returns a code generation error.
320103 LabVIEW crashes when compiling an FPGA VI containing an error cluster wired to a Boolean function.
310755 FIFO Name Discrepancies may Cause Error -61206
313940 The Mean,Variance, and Standard Deviation Express VI may Return Invalid Values
357204 Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
Installation and Activation
236642 LabVIEW's install directory can't have multibyte characters for the Xilinx tools to work.
306365 Some Xilinx IP palette functions require separate licensing from Xilinx
LabVIEW Project
223670 Compiling a VI in one FPGA context creates a code generation error if the VI is open and broken in another FPGA context.
277539 FPGA VI remains running on the target while the VI is open in edit mode.
304855 Editing project items causes LabVIEW to search for missing VIs.
Miscellaneous
172016 Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server
226029 The behavior of the Run button can be confusing when using the THIRD_PARTY_SIMULATION conditional disable symbol.
197816 Virtex 6 design with PLLs simulation run forever
Performance
236075 R-Series simulation error when loading waveform script that includes DIO ports
287790 "Compile Worker has stopped working" error message on launch.
294273 Using long VI names may cause Error 6 during FPGA code generation.
300201 When using the NI-Farm toolkit and having a CompileWorker.exe with multiple simultaneous jobs there may be hangs.
304548 Compilation Status dialog is unresponsive after computer has hibernated or been disconnected from a large job
304799 If a compilation fails with a communication error, the bitfile may be lost.
Upgrade - Behavior Change
317617 Disabled Front Panel Items Use FPGA Resources
Upgrade - Migration
107560 Interrupt VIs saved to previous versions of LabVIEW are broken
257184 Upgrading with clocks from CLIP can change the configured clocks.
276311 Upgrading from LabVIEW FPGA 2009 may cause designs using DSP48E components to overmap.
284873 Upgrading host VIs saved with Execute VI on Development Computer causes prompt to find niLvFpgaEmulationMode.ctl.



ID Known Issue
Building and Distributing LabVIEW Applications
171971

Return
TCP must be installed
Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server.

Workaround: TCP must be installed.

Reported Version: 2009    Resolved Version: N/A    Added: 08/04/2009
93395
4GIHITXE


Return
Modifying conditional disable symbols requires recompile
If you modify the conditional disable symbols in a project, the FPGA Module requires you to recompile the FPGA VI even if the FPGA VI does not use Conditional Disable structures.

Workaround: Recompile the FPGA VI.

Reported Version: 8.5    Resolved Version: N/A    Added: 08/04/2009
95971

Return
Error compiling empty external clock loop
If you compile an FPGA VI that contains only an empty loop configured to use an external clock, the FPGA Module returns an error.

Workaround: Do not compile an FPGA VI that contains only an empty loop configured to use an external clock.

Reported Version: Saturn    Resolved Version: N/A    Added: 08/04/2009
308548

Return
The Xilinx map program can crash if a file named "map" can be found anywhere on your system path.
When LabVIEW FPGA is running a compile, if a file named "map" can be found anywhere on your system path, then compilation will fail partway through. When compilation fails for this reason, the Xilinx log will contain an error with a message similar to the following: C:\PROGRA~2\MICROS~1.0\VC\include\map' is not recognized as an internal or external command, operable program or batch file. Process "Map" failed

Workaround: There are two workarounds. 1. Make a copy of the map.exe executables in your Xilinx bin directories. For example, for Xilinx 12.4 32-bit and 64-bit, make a copy of c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt\map.exe in c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt\map and a copy of c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt64\map.exe in c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt64\map. 2. Remove from your system path any directories that have files whose names match those of Xilinx executables but have no extension (i.e. map, par, trce, coregen). Restart the compile worker if it is running.

Reported Version: 2011    Resolved Version: N/A    Added: 07/10/2012
247993

Return
Removing a C-Series Module in a Project Forces Recompilation
Removing a module from a Chassis in a LabVIEW FPGA Project will force a recompilation, even if all VIs in the Build Specification's hierarchy do not reference the module.

Workaround: NA

Reported Version: 2010    Resolved Version: N/A    Added: 07/11/2012
354689

Return
Customer designs may fail with an over-mapping error if Output data and enable are synchronous to different clocks
Users can place Output Data and Enable nodes in different clock domains. This results in a Tri-state buffer on the FPGA that is enabled by a signal in the different clock domain than the data signal. Some FPGA families may not support this configuration, and user's design may fail to compile with an over-mapping error in some situations. For a Virtex 2 compile, the error may look similar to the attached Compilation Error.png file. The situation where it might fail for Virtex 2 is when two IO Nodes are mapped over two adjacent IOBs and the Data and Enable flops for the IOs are synchronous to 3 or more different clocks.

Workaround: The workaround is to modify the VI. Move the Output Enable node into the same clock domain as the Output Data node.

Reported Version: 8.2    Resolved Version: N/A    Added: 07/11/2012
313960

Return
DSP48s Are Not Properly Optimized with Integer Constants in LabVIEW FPGA 2011
LabVIEW FPGA 2011 does not properly optimize the amount of DSP48s in some cases. Unused data bits in integer constants cause more DSP48s to be used than are necessary. This can cause timing and resource utilization errors during compilation.

Workaround: In place of integer constants use fixed point (FXP) constants when wired to functions that require DSP48s. LabVIEW handles DSP48 optimization for FXP numbers better than integers.

Reported Version: 2011    Resolved Version: 2012    Added: 07/12/2012
Compatibility
156070

Return
Save for Previous of FPGA IO Nodes from 2009 and later to 8.6 and earlier can cause broken run arrow.
When performing a Save for Previous on FPGA projects containing IO items that are in version 2009 or later, IO Nodes can break when converting to version 8.6 and earlier.

Workaround: Redrop IO Nodes.

Reported Version: 9.0 - 2.1 branch    Resolved Version: N/A    Added: 08/02/2011
288024

Return
VI-defined memory loses initial values after Save for Previous for 8.6 and earlier.
When saving an FPGA project from version 2009 or later to version 8.6 or earlier, VI-defined memory items lose any initial values.

Workaround: Recreate the initial values in the previous version.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
Controls and Indicators
307714

Return
Silver controls are not available on Controls palette in FPGA VI context.
The Silver controls palette is not available for VIs opened under an FPGA target.

Workaround: Create controls/indicators on VIs under the My Computer context and then move the VI to the FPGA context.

Reported Version: 2011    Resolved Version: 2011 SP1    Added: 08/02/2011
External Code
238241

Return
When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.
When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.

Workaround: The wizard only extracts information from the top-level VHDL file, so add another VHDL wrapper that instantiates the original wrapper. In the new wrapper, do not mention the entity attribute.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
283397

Return
All CLIP vhd files must have a lowercase vhd extension.
CLIP vhd files are required to have a lower case extension or there will be an odd behavior during compiles.

Workaround: Define the VHD files with a lower case extension in the clip XML file.

Reported Version: 2010    Resolved Version: 2012    Added: 08/02/2011
303501

Return
Xilinx compile errors occur when using the IP Integration Node to integrate VHDL with string constants defined in package files in the generic and/or port declaration.
When you use IP Integration Node to wrap your IP and the top-level VHDL has constants or types in the generic and/or port declaration which are defined in your package files, a Xilinx error will be reported saying that the string constants are not declared when you compile.

Workaround: Add full namespace to the string constants in the generic and/or port declaration of the top-level VHDL.

Reported Version: 2011    Resolved Version: N/A    Added: 08/02/2011
304569

Return
The post-synthesis model of a ngc file will fail to simulate if the file name of the ngc file is different from the ngc component name.
When performing cycle accurate simulation with IP Integration node, the post-synthesis model of a ngc file will fail to simulate if the file name of the ngc file is different from the ngc component name.

Workaround: Make sure the ngc file name is the name of the ngc component name.

Reported Version: 2011    Resolved Version: N/A    Added: 08/02/2011
297138

Return
The length of the port name in the top-level VHDL file of a CLIP should not exceed 22 letters.
The length of the port name in the top-level VHDL file of a CLIP should not exceed 22 letters. Or else, the long name will be truncated by LabVIEW FPGA, which will lead to compilation failure.

Workaround: Change the port name to be shorter than 22 letters.

Reported Version: 2010    Resolved Version: 2012    Added: 03/06/2012
300339

Return
Estimated Device Utilization Incorrect or Not Available for Certain Projects and Targets
Projects for NI FlexRIO targets or projects with user-defined IP that includes pre-compiled netlists (such as .ngc files) may show incorrect results in the "Estimated device utilization (pre-synthesis)" report. The numbers shown of used slice registers and slice LUTs may be smaller-than-expected (possible even zero).

Workaround: This problem only affects "pre-synthesis" resource estimations. Correct utilization data can always be obtained by compiling the project, which provides both the correct "Estimated device utilization (synthesis)" and "Final device utilization (map)" reports. If the "pre-synthesis" estimated results are absolutely necessary, the correct pre-synthesis estimation of used slice registers and slice LUTs can be found within the Xilinx log at the end of the PlanAhead section and before XstSynthesis.

Reported Version: 2011    Resolved Version: 2012    Added: 03/06/2012
357304

Return
LabVIEW FPGA Derived Clocks Do Not Behave Properly Within FlexRIO Adapter Module CLIP
The enable signal to a BUFGCE of a derived clock requires the derived clock to be preset (out of a BUFG from the DCM). This is problematic because the adapter module goes through a power cycle during the download, reset, and close with reset methods. This causes the external clock from CLIP to shut off, and the clock remains turned off until sometime after the adapter module resumes power. In Short: 1. When reset is asserted, the FAM CLIP disables it's clock, and the derived clock's BUFGCE is still enabled even though there is no clock at the input of the DCM. 2. The derived clock valid signal remains high out of reset even though the CLIP has the source clock valid signal low (it's reset state) and has not yet supplied a clock.

Workaround: Derive all needed clocks within the CLIP itself and disable support for user derived clocks in LabVIEW FPGA via the CLIP XML.

Reported Version: 2011    Resolved Version: N/A    Added: 07/09/2012
Functions, VIs, and Express VIs
150867

Return
"Not supported for current target" message may occur when Preallocate Arrays is not set.
The "Not supported for current target" error may be displayed for FPGA Analysis functions when the FPGA Preallocate Arrays option is not set. The actual error is that this option must be selected.

Workaround: In VI Properties check the Preallocate Arrays option.

Reported Version: 8.6.1    Resolved Version: N/A    Added: 08/02/2011
151047

Return
High-Throughput Math Library node fails to compile if pipeline stage exceeds 64
If the number of pipeline stages exceeds 64, the compile will report "Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more." This usually happens in configurations of high-throughput math library nodes where the output data width is 64 and throughput is 1 cycle/sample inside SCTL.

Workaround: Reduce the pipeline stages by reducing the output word length or the throughput. If more than 64 pipeline stages are needed, please contact National Instruments support.

Reported Version: 2009    Resolved Version: N/A    Added: 08/02/2011
217824

Return
FIFOs with built-in control are not supported with cycle-accurate simulation.
When attempting to use full diagram simulation on a design using FIFOs with built-in control logic, there is no simulation model for these elements.

Workaround: Use a conditional disable structure around the built-in FIFOs when using full diagram simulation.

Reported Version: 2010    Resolved Version: 2012    Added: 08/02/2011
232504

Return
Compilation on Spartan-6 FPGAs fails when compound add is placed before Loop Condition terminal.
Compilations for Spartan-6 targets can fail is a compound add function is placed directly before the Loop Condition terminal in a single-cycle timed loop.

Workaround: Change number of inputs to compound add to an even number or replace with regular add functions.

Reported Version: 2010    Resolved Version: 2012    Added: 08/02/2011
296185

Return
Interleaving two arrays with different fixed-point configurations returns a code generation error.
When using the Interleave Arrays function on a LabVIEW FPGA VI, if the arrays are of the same fixed length, but the fixed-point configurations of the elements are different, code generation will fail.

Workaround: Change the fixed point configuration of the two arrays to be the same using "To Fixed-Point".

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
320103

Return
LabVIEW crashes when compiling an FPGA VI containing an error cluster wired to a Boolean function.
A new feature added to LabVIEW 2011 was the ability to wire an error cluster directly to a Boolean function. Compiling an FPGA VI that contains this feature will cause LabVIEW to crash.

Workaround: Unbundle the error wire and wire the status element to the Boolean function manually.

Reported Version: 2011    Resolved Version: 2012    Added: 03/05/2012
310755

Return
FIFO Name Discrepancies may Cause Error -61206
If a DMA FIFO has a mismatch in capitalization between its name and what the FPGA interface expects, then error -61206: "The configured item does not exist".

Workaround: Use lower case letters for FIFO names

Reported Version: 2011    Resolved Version: N/A    Added: 07/10/2012
313940

Return
The Mean,Variance, and Standard Deviation Express VI may Return Invalid Values
Due to a roundoff error that may occur with small variance values, the Mean,Variance, and Standard Deviation Express VI may return incorrect results.

Workaround: Edit the SubVI to adapt it to a configuration that meets your application's specific needs. For more information, please see the following forum thread: http://forums.ni.com/t5/LabVIEW/labview-2010-FPGA-problem-with-mean-variance-SubVI/td-p/1659110

Reported Version: 2011    Resolved Version: N/A    Added: 07/10/2012
357204

Return
Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
The Compound Arithmetic function may execute operations in a different order on the FPGA than on the desktop, producing slightly different results for floating-point operations. The differences include small rounding discrepancies as well as NaN and Inf behavior.

Workaround: Decompose the Compound Arithmetic Function into individual arithmetic functions to force the order of operations to conform to what you expect.

Reported Version: 2012 32-bit    Resolved Version: N/A    Added: 07/10/2012
Installation and Activation
236642

Return
LabVIEW's install directory can't have multibyte characters for the Xilinx tools to work.
Local compiles with the Xilinx tools are not possible if LabVIEW's directory contains multibyte characters. If it is the default program files windows path then everything will work fine.

Workaround: You can use the remote compile feature to use another machine to do your compilations if you run into this issue. It can be a Japanese machine, just make sure that the LabVIEW directory doesn't have multibyte characters.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
306365

Return
Some Xilinx IP palette functions require separate licensing from Xilinx
For some functions on the Xilinx IP palette, when launching Xilinx CoreGenerator, you may see a dialog indicating the core is not licensed. To obtain licenses for these cores, visit http://www.xilinx.com/products/intellectual-property/index.htm.

Workaround: NA

Reported Version: 2011    Resolved Version: N/A    Added: 08/02/2011
LabVIEW Project
223670

Return
Compiling a VI in one FPGA context creates a code generation error if the VI is open and broken in another FPGA context.
The compilation of a VI may return an error saying the VI is broken if the same VI is open and broken in another FPGA context. The error occurs at the beginning of stage 1 of the compilation.

Workaround: Close the broken copies of the VI in the other FPGA contexts.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
277539

Return
FPGA VI remains running on the target while the VI is open in edit mode.
While the top-level FPGA VI is running, you can open a reentrant SubVI from the block diagram and change to edit-mode from the clone. If you break the SubVI in edit-mode, the top-level FPGA VI will also break, but the VI will remain running on the target. If you fix the SubVI, both VIs will no longer be broken and the FPGA VI cannot be stopped.

Workaround: Reboot the target.

Reported Version: 2010    Resolved Version: 2012    Added: 08/02/2011
304855

Return
Editing project items causes LabVIEW to search for missing VIs.
Editing project items under an FPGA target can cause LabVIEW to search for VIs included in the project under the FPGA target if the VI cannot be found on disk.

Workaround: Remove the missing VI from the project or update the project to load the VI from the correct location.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
Miscellaneous
172016

Return
Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server
If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality.

Workaround: Refer to the KnowledgeBase (http://digital.ni.com/public.nsf/websearch/91A1EA23DB25BE4386256E54007AE9E8?OpenDocument) for more information about correcting this problem.

Reported Version: 2009    Resolved Version: N/A    Added: 08/04/2009
226029

Return
The behavior of the Run button can be confusing when using the THIRD_PARTY_SIMULATION conditional disable symbol.
Errors that normally break the Run button will not break the Run button if the error occurs within a Conditional Disable structure case defined for THIRD_PARTY_SIMULATION. In this case, you cannot build simulation exports, but you can build other build specifications. In addition, if the VI has errors outside the simulation-specific case and the Run button is broken, you will not be able to build a Simulation Export build specification.

Workaround: * If the Run button is not broken but the simulation-specific code contains errors, LabVIEW produces code generation errors when you try to build the Simulation Export build specification. Fix the broken code before building the simulation export. * If the Run button is broken because of code outside of a case defined for THIRD_PARTY_SIMULATION , you have the following options to work around the issue before building a Simulation Export build specification: 1) Fix the error condition in the code. 2) Use the Diagram Disable structure to disable the broken or target-specific code. 3) Define your own custom conditional disable symbol in the project for the FPGA target you are using, and place the broken code in that case of the Conditional Disable structure.

Reported Version: 2010 32-bit    Resolved Version: N/A    Added: 08/02/2011
197816

Return
Virtex 6 design with PLLs simulation run forever
Currently there is not a mechanism to stop the Virtex 6 PLL from running, which can cause the simulation to continue running when the "Run All" command is used in the simulator.

Workaround: You can use one of the following options to stop the simulation: * Add an assertion failure to the of end your test bench. * Run the test bench for a specified amount of time.

Reported Version: 2010    Resolved Version: N/A    Added: 07/11/2012
Performance
236075

Return

R-Series simulation error when loading waveform script that includes DIO ports
The following error can be reported when loading a waveform that includes R Series DIO configured as ports. # ** Error: (vish-4014) No objects found matching 'tb_NiFpgaSimulationModel/NiFpgaSimulationModel_Instance

/TargetTopLevelSim_Instance/thewindowx/thevi/../Conn0Port0'.

Workaround: Use DIO lines instead of ports in the FPGA VI.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
287790

Return
"Compile Worker has stopped working" error message on launch.
When launching the Compile Worker for the first time after installation, this error may occur due to a bug in the .NET framework causing a hang.

Workaround: Restart the Compile Worker.

Reported Version: 2011    Resolved Version: N/A    Added: 08/02/2011
294273

Return
Using long VI names may cause Error 6 during FPGA code generation.
If a VI name or path is too long, you may see the following error during code generation: Error 6:Copy VI Hierarchy With FPGA Side Effects

Workaround: Shorten the FPGA VI name or path.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
300201

Return
When using the NI-Farm toolkit and having a CompileWorker.exe with multiple simultaneous jobs there may be hangs.
When using the NI-Farm toolkit with a single CompileWorker.exe compiling simultaneous jobs, it is possible for one or more of the jobs to hang.

Workaround: Restart the hung job.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
304548

Return
Compilation Status dialog is unresponsive after computer has hibernated or been disconnected from a large job
When compiling on a remote machine, if client computer disconnects or goes into hibernation (sleep), the Compilation Status dialog may become unresponsive after reconnecting or when the client computer wakes up. The Elapsed Time may still be increasing, and the status icon may be spinning rapidly. LabVIEW will be using more memory and more CPU resources. Other VIs and project windows in LabVIEW should still be responsive.

Workaround: Save all your files and restart LabVIEW. Open the corresponding project, right-click on the Build Specification, and choose Reconnect to Compilation. You should be able to retrieve your compilation and create a bitfile.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
304799

Return
If a compilation fails with a communication error, the bitfile may be lost.
If a communication error occurs while compiling a LabVIEW FPGA VI, it is possible you may not be able to reconnect to the compilation.

Workaround: Rebuild the LabVIEW FPGA VI.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
Upgrade - Behavior Change
317617

Return
Disabled Front Panel Items Use FPGA Resources
Front Panel Array Items that are located within a disabled state of a diagram disable structure are not removed before compilation. This change is a result of a bug-fix that brought LabVIEW FPGA into line with standard LabVIEW behavior. The implications of this are two-fold: 1. You may now run into resource over-mapping compilation errors, especially if large array items are present on the Front Panel. 2. You may now run into timing violation compilation errors if a Front Panel item is tied to a fixed resource within a Single Cycle Timed Loop due to routing delays between fixed resources (I/O)

Workaround: N/A

Reported Version: 2011    Resolved Version: N/A    Added: 07/11/2012
Upgrade - Migration
107560

Return
Interrupt VIs saved to previous versions of LabVIEW are broken
If you save an FPGA VI that contains an Interrupt VI to a previous version of LabVIEW and open the FPGA VI in a previous version of LabVIEW, the FPGA VI is broken because the Interrupt VI is not executable.

Workaround: You can delete the Interrupt VI and replace it with an Interrupt VI from the current version to resolve the issue.

Reported Version: Saturn    Resolved Version: N/A    Added: 08/04/2009
257184

Return
Upgrading with clocks from CLIP can change the configured clocks.
When upgrading, if a design uses CLIP clocks, the configuration of these clocks may be reset.

Workaround: Reconfigure the CLIP clocks in the project.

Reported Version: 2010    Resolved Version: 2012    Added: 08/02/2011
276311

Return
Upgrading from LabVIEW FPGA 2009 may cause designs using DSP48E components to overmap.
When upgrading from LabVIEW FPGA 2009, it is possible that designs that fit on the FPGA target previously will fail to compile due to overmapping of DSP48E components. This is due to a change in the Xilinx compile process from version 10.1 to 11.x and later.

Workaround: Use High-Throughput multiplies configured to use Look-Up Tables to reduce the number of DSP48Es used for multiplication functions.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
284873

Return
Upgrading host VIs saved with Execute VI on Development Computer causes prompt to find niLvFpgaEmulationMode.ctl.
When a host VI was last saved with the FPGA target configured to Execute VI on Development Computer, a search dialog will be displayed looking for niLvFpgaEmulationMode.ctl.

Workaround: Reconfigure the target to execute on the FPGA and then back to the development computer.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011

Known Issues by Date

The following items are known issues in LabVIEW 2010 and 2010SP1 FPGA Module sorted by Date.

107560 Interrupt VIs saved to previous versions of LabVIEW are broken
171971 TCP must be installed
172016 Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server
93395 4GIHITXE Modifying conditional disable symbols requires recompile
95971 Error compiling empty external clock loop
150867 "Not supported for current target" message may occur when Preallocate Arrays is not set.
151047 High-Throughput Math Library node fails to compile if pipeline stage exceeds 64
156070 Save for Previous of FPGA IO Nodes from 2009 and later to 8.6 and earlier can cause broken run arrow.
217824 FIFOs with built-in control are not supported with cycle-accurate simulation.
223670 Compiling a VI in one FPGA context creates a code generation error if the VI is open and broken in another FPGA context.
226029 The behavior of the Run button can be confusing when using the THIRD_PARTY_SIMULATION conditional disable symbol.
232504 Compilation on Spartan-6 FPGAs fails when compound add is placed before Loop Condition terminal.
236075 R-Series simulation error when loading waveform script that includes DIO ports
236642 LabVIEW's install directory can't have multibyte characters for the Xilinx tools to work.
238241 When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.
257184 Upgrading with clocks from CLIP can change the configured clocks.
276311 Upgrading from LabVIEW FPGA 2009 may cause designs using DSP48E components to overmap.
277539 FPGA VI remains running on the target while the VI is open in edit mode.
283397 All CLIP vhd files must have a lowercase vhd extension.
284873 Upgrading host VIs saved with Execute VI on Development Computer causes prompt to find niLvFpgaEmulationMode.ctl.
287790 "Compile Worker has stopped working" error message on launch.
288024 VI-defined memory loses initial values after Save for Previous for 8.6 and earlier.
294273 Using long VI names may cause Error 6 during FPGA code generation.
296185 Interleaving two arrays with different fixed-point configurations returns a code generation error.
300201 When using the NI-Farm toolkit and having a CompileWorker.exe with multiple simultaneous jobs there may be hangs.
303501 Xilinx compile errors occur when using the IP Integration Node to integrate VHDL with string constants defined in package files in the generic and/or port declaration.
304548 Compilation Status dialog is unresponsive after computer has hibernated or been disconnected from a large job
304569 The post-synthesis model of a ngc file will fail to simulate if the file name of the ngc file is different from the ngc component name.
304799 If a compilation fails with a communication error, the bitfile may be lost.
304855 Editing project items causes LabVIEW to search for missing VIs.
306365 Some Xilinx IP palette functions require separate licensing from Xilinx
307714 Silver controls are not available on Controls palette in FPGA VI context.
320103 LabVIEW crashes when compiling an FPGA VI containing an error cluster wired to a Boolean function.
297138 The length of the port name in the top-level VHDL file of a CLIP should not exceed 22 letters.
300339 Estimated Device Utilization Incorrect or Not Available for Certain Projects and Targets
357304 LabVIEW FPGA Derived Clocks Do Not Behave Properly Within FlexRIO Adapter Module CLIP
308548 The Xilinx map program can crash if a file named "map" can be found anywhere on your system path.
310755 FIFO Name Discrepancies may Cause Error -61206
313940 The Mean,Variance, and Standard Deviation Express VI may Return Invalid Values
357204 Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
197816 Virtex 6 design with PLLs simulation run forever
247993 Removing a C-Series Module in a Project Forces Recompilation
317617 Disabled Front Panel Items Use FPGA Resources
354689 Customer designs may fail with an over-mapping error if Output data and enable are synchronous to different clocks
313960 DSP48s Are Not Properly Optimized with Integer Constants in LabVIEW FPGA 2011



ID Known Issue
107560

Return
Interrupt VIs saved to previous versions of LabVIEW are broken
If you save an FPGA VI that contains an Interrupt VI to a previous version of LabVIEW and open the FPGA VI in a previous version of LabVIEW, the FPGA VI is broken because the Interrupt VI is not executable.

Workaround: You can delete the Interrupt VI and replace it with an Interrupt VI from the current version to resolve the issue.

Reported Version: Saturn    Resolved Version: N/A    Added: 08/04/2009
171971

Return
TCP must be installed
Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server.

Workaround: TCP must be installed.

Reported Version: 2009    Resolved Version: N/A    Added: 08/04/2009
172016

Return
Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server
If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality.

Workaround: Refer to the KnowledgeBase (http://digital.ni.com/public.nsf/websearch/91A1EA23DB25BE4386256E54007AE9E8?OpenDocument) for more information about correcting this problem.

Reported Version: 2009    Resolved Version: N/A    Added: 08/04/2009
93395
4GIHITXE


Return
Modifying conditional disable symbols requires recompile
If you modify the conditional disable symbols in a project, the FPGA Module requires you to recompile the FPGA VI even if the FPGA VI does not use Conditional Disable structures.

Workaround: Recompile the FPGA VI.

Reported Version: 8.5    Resolved Version: N/A    Added: 08/04/2009
95971

Return
Error compiling empty external clock loop
If you compile an FPGA VI that contains only an empty loop configured to use an external clock, the FPGA Module returns an error.

Workaround: Do not compile an FPGA VI that contains only an empty loop configured to use an external clock.

Reported Version: Saturn    Resolved Version: N/A    Added: 08/04/2009
150867

Return
"Not supported for current target" message may occur when Preallocate Arrays is not set.
The "Not supported for current target" error may be displayed for FPGA Analysis functions when the FPGA Preallocate Arrays option is not set. The actual error is that this option must be selected.

Workaround: In VI Properties check the Preallocate Arrays option.

Reported Version: 8.6.1    Resolved Version: N/A    Added: 08/02/2011
151047

Return
High-Throughput Math Library node fails to compile if pipeline stage exceeds 64
If the number of pipeline stages exceeds 64, the compile will report "Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more." This usually happens in configurations of high-throughput math library nodes where the output data width is 64 and throughput is 1 cycle/sample inside SCTL.

Workaround: Reduce the pipeline stages by reducing the output word length or the throughput. If more than 64 pipeline stages are needed, please contact National Instruments support.

Reported Version: 2009    Resolved Version: N/A    Added: 08/02/2011
156070

Return
Save for Previous of FPGA IO Nodes from 2009 and later to 8.6 and earlier can cause broken run arrow.
When performing a Save for Previous on FPGA projects containing IO items that are in version 2009 or later, IO Nodes can break when converting to version 8.6 and earlier.

Workaround: Redrop IO Nodes.

Reported Version: 9.0 - 2.1 branch    Resolved Version: N/A    Added: 08/02/2011
217824

Return
FIFOs with built-in control are not supported with cycle-accurate simulation.
When attempting to use full diagram simulation on a design using FIFOs with built-in control logic, there is no simulation model for these elements.

Workaround: Use a conditional disable structure around the built-in FIFOs when using full diagram simulation.

Reported Version: 2010    Resolved Version: 2012    Added: 08/02/2011
223670

Return
Compiling a VI in one FPGA context creates a code generation error if the VI is open and broken in another FPGA context.
The compilation of a VI may return an error saying the VI is broken if the same VI is open and broken in another FPGA context. The error occurs at the beginning of stage 1 of the compilation.

Workaround: Close the broken copies of the VI in the other FPGA contexts.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
226029

Return
The behavior of the Run button can be confusing when using the THIRD_PARTY_SIMULATION conditional disable symbol.
Errors that normally break the Run button will not break the Run button if the error occurs within a Conditional Disable structure case defined for THIRD_PARTY_SIMULATION. In this case, you cannot build simulation exports, but you can build other build specifications. In addition, if the VI has errors outside the simulation-specific case and the Run button is broken, you will not be able to build a Simulation Export build specification.

Workaround: * If the Run button is not broken but the simulation-specific code contains errors, LabVIEW produces code generation errors when you try to build the Simulation Export build specification. Fix the broken code before building the simulation export. * If the Run button is broken because of code outside of a case defined for THIRD_PARTY_SIMULATION , you have the following options to work around the issue before building a Simulation Export build specification: 1) Fix the error condition in the code. 2) Use the Diagram Disable structure to disable the broken or target-specific code. 3) Define your own custom conditional disable symbol in the project for the FPGA target you are using, and place the broken code in that case of the Conditional Disable structure.

Reported Version: 2010 32-bit    Resolved Version: N/A    Added: 08/02/2011
232504

Return
Compilation on Spartan-6 FPGAs fails when compound add is placed before Loop Condition terminal.
Compilations for Spartan-6 targets can fail is a compound add function is placed directly before the Loop Condition terminal in a single-cycle timed loop.

Workaround: Change number of inputs to compound add to an even number or replace with regular add functions.

Reported Version: 2010    Resolved Version: 2012    Added: 08/02/2011
236075

Return

R-Series simulation error when loading waveform script that includes DIO ports
The following error can be reported when loading a waveform that includes R Series DIO configured as ports. # ** Error: (vish-4014) No objects found matching 'tb_NiFpgaSimulationModel/NiFpgaSimulationModel_Instance

/TargetTopLevelSim_Instance/thewindowx/thevi/../Conn0Port0'.

Workaround: Use DIO lines instead of ports in the FPGA VI.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
236642

Return
LabVIEW's install directory can't have multibyte characters for the Xilinx tools to work.
Local compiles with the Xilinx tools are not possible if LabVIEW's directory contains multibyte characters. If it is the default program files windows path then everything will work fine.

Workaround: You can use the remote compile feature to use another machine to do your compilations if you run into this issue. It can be a Japanese machine, just make sure that the LabVIEW directory doesn't have multibyte characters.
Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
238241

Return
When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.
When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page.

Workaround: The wizard only extracts information from the top-level VHDL file, so add another VHDL wrapper that instantiates the original wrapper. In the new wrapper, do not mention the entity attribute.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
257184

Return
Upgrading with clocks from CLIP can change the configured clocks.
When upgrading, if a design uses CLIP clocks, the configuration of these clocks may be reset.

Workaround: Reconfigure the CLIP clocks in the project.

Reported Version: 2010    Resolved Version: 2012    Added: 08/02/2011
276311

Return
Upgrading from LabVIEW FPGA 2009 may cause designs using DSP48E components to overmap.
When upgrading from LabVIEW FPGA 2009, it is possible that designs that fit on the FPGA target previously will fail to compile due to overmapping of DSP48E components. This is due to a change in the Xilinx compile process from version 10.1 to 11.x and later.

Workaround: Use High-Throughput multiplies configured to use Look-Up Tables to reduce the number of DSP48Es used for multiplication functions.

Reported Version: 2010    Resolved Version: N/A    Added: 08/02/2011
277539

Return
FPGA VI remains running on the target while the VI is open in edit mode.
While the top-level FPGA VI is running, you can open a reentrant SubVI from the block diagram and change to edit-mode from the clone. If you break the SubVI in edit-mode, the top-level FPGA VI will also break, but the VI will remain running on the target. If you fix the SubVI, both VIs will no longer be broken and the FPGA VI cannot be stopped.

Workaround: Reboot the target.

Reported Version: 2010    Resolved Version: 2012    Added: 08/02/2011
283397

Return
All CLIP vhd files must have a lowercase vhd extension.
CLIP vhd files are required to have a lower case extension or there will be an odd behavior during compiles.

Workaround: Define the VHD files with a lower case extension in the clip XML file.

Reported Version: 2010    Resolved Version: 2012    Added: 08/02/2011
284873

Return
Upgrading host VIs saved with Execute VI on Development Computer causes prompt to find niLvFpgaEmulationMode.ctl.
When a host VI was last saved with the FPGA target configured to Execute VI on Development Computer, a search dialog will be displayed looking for niLvFpgaEmulationMode.ctl.

Workaround: Reconfigure the target to execute on the FPGA and then back to the development computer.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
287790

Return
"Compile Worker has stopped working" error message on launch.
When launching the Compile Worker for the first time after installation, this error may occur due to a bug in the .NET framework causing a hang.

Workaround: Restart the Compile Worker.

Reported Version: 2011    Resolved Version: N/A    Added: 08/02/2011
288024

Return
VI-defined memory loses initial values after Save for Previous for 8.6 and earlier.
When saving an FPGA project from version 2009 or later to version 8.6 or earlier, VI-defined memory items lose any initial values.

Workaround: Recreate the initial values in the previous version.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
294273

Return
Using long VI names may cause Error 6 during FPGA code generation.
If a VI name or path is too long, you may see the following error during code generation: Error 6:Copy VI Hierarchy With FPGA Side Effects

Workaround: Shorten the FPGA VI name or path.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
296185

Return
Interleaving two arrays with different fixed-point configurations returns a code generation error.
When using the Interleave Arrays function on a LabVIEW FPGA VI, if the arrays are of the same fixed length, but the fixed-point configurations of the elements are different, code generation will fail.

Workaround: Change the fixed point configuration of the two arrays to be the same using "To Fixed-Point".

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
300201

Return
When using the NI-Farm toolkit and having a CompileWorker.exe with multiple simultaneous jobs there may be hangs.
When using the NI-Farm toolkit with a single CompileWorker.exe compiling simultaneous jobs, it is possible for one or more of the jobs to hang.

Workaround: Restart the hung job.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
303501

Return
Xilinx compile errors occur when using the IP Integration Node to integrate VHDL with string constants defined in package files in the generic and/or port declaration.
When you use IP Integration Node to wrap your IP and the top-level VHDL has constants or types in the generic and/or port declaration which are defined in your package files, a Xilinx error will be reported saying that the string constants are not declared when you compile.

Workaround: Add full namespace to the string constants in the generic and/or port declaration of the top-level VHDL.

Reported Version: 2011    Resolved Version: N/A    Added: 08/02/2011
304548

Return
Compilation Status dialog is unresponsive after computer has hibernated or been disconnected from a large job
When compiling on a remote machine, if client computer disconnects or goes into hibernation (sleep), the Compilation Status dialog may become unresponsive after reconnecting or when the client computer wakes up. The Elapsed Time may still be increasing, and the status icon may be spinning rapidly. LabVIEW will be using more memory and more CPU resources. Other VIs and project windows in LabVIEW should still be responsive.

Workaround: Save all your files and restart LabVIEW. Open the corresponding project, right-click on the Build Specification, and choose Reconnect to Compilation. You should be able to retrieve your compilation and create a bitfile.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
304569

Return
The post-synthesis model of a ngc file will fail to simulate if the file name of the ngc file is different from the ngc component name.
When performing cycle accurate simulation with IP Integration node, the post-synthesis model of a ngc file will fail to simulate if the file name of the ngc file is different from the ngc component name.

Workaround: Make sure the ngc file name is the name of the ngc component name.

Reported Version: 2011    Resolved Version: N/A    Added: 08/02/2011
304799

Return
If a compilation fails with a communication error, the bitfile may be lost.
If a communication error occurs while compiling a LabVIEW FPGA VI, it is possible you may not be able to reconnect to the compilation.

Workaround: Rebuild the LabVIEW FPGA VI.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
304855

Return
Editing project items causes LabVIEW to search for missing VIs.
Editing project items under an FPGA target can cause LabVIEW to search for VIs included in the project under the FPGA target if the VI cannot be found on disk.

Workaround: Remove the missing VI from the project or update the project to load the VI from the correct location.

Reported Version: 2011    Resolved Version: 2012    Added: 08/02/2011
306365

Return
Some Xilinx IP palette functions require separate licensing from Xilinx
For some functions on the Xilinx IP palette, when launching Xilinx CoreGenerator, you may see a dialog indicating the core is not licensed. To obtain licenses for these cores, visit http://www.xilinx.com/products/intellectual-property/index.htm.

Workaround: NA

Reported Version: 2011    Resolved Version: N/A    Added: 08/02/2011
307714

Return
Silver controls are not available on Controls palette in FPGA VI context.
The Silver controls palette is not available for VIs opened under an FPGA target.

Workaround: Create controls/indicators on VIs under the My Computer context and then move the VI to the FPGA context.

Reported Version: 2011    Resolved Version: 2011 SP1    Added: 08/02/2011
320103

Return
LabVIEW crashes when compiling an FPGA VI containing an error cluster wired to a Boolean function.
A new feature added to LabVIEW 2011 was the ability to wire an error cluster directly to a Boolean function. Compiling an FPGA VI that contains this feature will cause LabVIEW to crash.

Workaround: Unbundle the error wire and wire the status element to the Boolean function manually.

Reported Version: 2011    Resolved Version: 2012    Added: 03/05/2012
297138

Return
The length of the port name in the top-level VHDL file of a CLIP should not exceed 22 letters.
The length of the port name in the top-level VHDL file of a CLIP should not exceed 22 letters. Or else, the long name will be truncated by LabVIEW FPGA, which will lead to compilation failure.

Workaround: Change the port name to be shorter than 22 letters.

Reported Version: 2010    Resolved Version: 2012    Added: 03/06/2012
300339

Return
Estimated Device Utilization Incorrect or Not Available for Certain Projects and Targets
Projects for NI FlexRIO targets or projects with user-defined IP that includes pre-compiled netlists (such as .ngc files) may show incorrect results in the "Estimated device utilization (pre-synthesis)" report. The numbers shown of used slice registers and slice LUTs may be smaller-than-expected (possible even zero).

Workaround: This problem only affects "pre-synthesis" resource estimations. Correct utilization data can always be obtained by compiling the project, which provides both the correct "Estimated device utilization (synthesis)" and "Final device utilization (map)" reports. If the "pre-synthesis" estimated results are absolutely necessary, the correct pre-synthesis estimation of used slice registers and slice LUTs can be found within the Xilinx log at the end of the PlanAhead section and before XstSynthesis.

Reported Version: 2011    Resolved Version: 2012    Added: 03/06/2012
357304

Return
LabVIEW FPGA Derived Clocks Do Not Behave Properly Within FlexRIO Adapter Module CLIP
The enable signal to a BUFGCE of a derived clock requires the derived clock to be preset (out of a BUFG from the DCM). This is problematic because the adapter module goes through a power cycle during the download, reset, and close with reset methods. This causes the external clock from CLIP to shut off, and the clock remains turned off until sometime after the adapter module resumes power. In Short: 1. When reset is asserted, the FAM CLIP disables it's clock, and the derived clock's BUFGCE is still enabled even though there is no clock at the input of the DCM. 2. The derived clock valid signal remains high out of reset even though the CLIP has the source clock valid signal low (it's reset state) and has not yet supplied a clock.

Workaround: Derive all needed clocks within the CLIP itself and disable support for user derived clocks in LabVIEW FPGA via the CLIP XML.

Reported Version: 2011    Resolved Version: N/A    Added: 07/09/2012
308548

Return
The Xilinx map program can crash if a file named "map" can be found anywhere on your system path.
When LabVIEW FPGA is running a compile, if a file named "map" can be found anywhere on your system path, then compilation will fail partway through. When compilation fails for this reason, the Xilinx log will contain an error with a message similar to the following: C:\PROGRA~2\MICROS~1.0\VC\include\map' is not recognized as an internal or external command, operable program or batch file. Process "Map" failed

Workaround: There are two workarounds. 1. Make a copy of the map.exe executables in your Xilinx bin directories. For example, for Xilinx 12.4 32-bit and 64-bit, make a copy of c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt\map.exe in c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt\map and a copy of c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt64\map.exe in c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt64\map. 2. Remove from your system path any directories that have files whose names match those of Xilinx executables but have no extension (i.e. map, par, trce, coregen). Restart the compile worker if it is running.

Reported Version: 2011    Resolved Version: N/A    Added: 07/10/2012
310755

Return
FIFO Name Discrepancies may Cause Error -61206
If a DMA FIFO has a mismatch in capitalization between its name and what the FPGA interface expects, then error -61206: "The configured item does not exist".

Workaround: Use lower case letters for FIFO names

Reported Version: 2011    Resolved Version: N/A    Added: 07/10/2012
313940

Return
The Mean,Variance, and Standard Deviation Express VI may Return Invalid Values
Due to a roundoff error that may occur with small variance values, the Mean,Variance, and Standard Deviation Express VI may return incorrect results.

Workaround: Edit the SubVI to adapt it to a configuration that meets your application's specific needs. For more information, please see the following forum thread: http://forums.ni.com/t5/LabVIEW/labview-2010-FPGA-problem-with-mean-variance-SubVI/td-p/1659110

Reported Version: 2011    Resolved Version: N/A    Added: 07/10/2012
357204

Return
Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
The Compound Arithmetic function may execute operations in a different order on the FPGA than on the desktop, producing slightly different results for floating-point operations. The differences include small rounding discrepancies as well as NaN and Inf behavior.

Workaround: Decompose the Compound Arithmetic Function into individual arithmetic functions to force the order of operations to conform to what you expect.

Reported Version: 2012 32-bit    Resolved Version: N/A    Added: 07/10/2012
197816

Return
Virtex 6 design with PLLs simulation run forever
Currently there is not a mechanism to stop the Virtex 6 PLL from running, which can cause the simulation to continue running when the "Run All" command is used in the simulator.

Workaround: You can use one of the following options to stop the simulation: * Add an assertion failure to the of end your test bench. * Run the test bench for a specified amount of time.

Reported Version: 2010    Resolved Version: N/A    Added: 07/11/2012
247993

Return
Removing a C-Series Module in a Project Forces Recompilation
Removing a module from a Chassis in a LabVIEW FPGA Project will force a recompilation, even if all VIs in the Build Specification's hierarchy do not reference the module.

Workaround: NA

Reported Version: 2010    Resolved Version: N/A    Added: 07/11/2012
317617

Return
Disabled Front Panel Items Use FPGA Resources
Front Panel Array Items that are located within a disabled state of a diagram disable structure are not removed before compilation. This change is a result of a bug-fix that brought LabVIEW FPGA into line with standard LabVIEW behavior. The implications of this are two-fold: 1. You may now run into resource over-mapping compilation errors, especially if large array items are present on the Front Panel. 2. You may now run into timing violation compilation errors if a Front Panel item is tied to a fixed resource within a Single Cycle Timed Loop due to routing delays between fixed resources (I/O)

Workaround: N/A

Reported Version: 2011    Resolved Version: N/A    Added: 07/11/2012
354689

Return
Customer designs may fail with an over-mapping error if Output data and enable are synchronous to different clocks
Users can place Output Data and Enable nodes in different clock domains. This results in a Tri-state buffer on the FPGA that is enabled by a signal in the different clock domain than the data signal. Some FPGA families may not support this configuration, and user's design may fail to compile with an over-mapping error in some situations. For a Virtex 2 compile, the error may look similar to the attached Compilation Error.png file. The situation where it might fail for Virtex 2 is when two IO Nodes are mapped over two adjacent IOBs and the Data and Enable flops for the IOs are synchronous to 3 or more different clocks.

Workaround: The workaround is to modify the VI. Move the Output Enable node into the same clock domain as the Output Data node.

Reported Version: 8.2    Resolved Version: N/A    Added: 07/11/2012
313960

Return
DSP48s Are Not Properly Optimized with Integer Constants in LabVIEW FPGA 2011
LabVIEW FPGA 2011 does not properly optimize the amount of DSP48s in some cases. Unused data bits in integer constants cause more DSP48s to be used than are necessary. This can cause timing and resource utilization errors during compilation.

Workaround: In place of integer constants use fixed point (FXP) constants when wired to functions that require DSP48s. LabVIEW handles DSP48 optimization for FXP numbers better than integers.

Reported Version: 2011    Resolved Version: 2012    Added: 07/12/2012

Document last updated on 7/12/2012

Back to Top

Bookmark & Share


Ratings

Rate this document

Answered Your Question?
Yes No

Submit