Since the inception of the PXI standard in 1997, NI has played a key role in building a foundation for innovation by continually delivering a broad and high-performance chassis portfolio to meet the I/O point and performance needs of customer applications. With the latest chassis release, NI has delivered the first PXI chassis based on PCI Express Gen 3 technology to offer engineers twice the slot and system bandwidth of previous generation chassis.
Chassis Technology at a Glance
- PXI Express with PCI Express Gen 3 technology
- 16 hybrid slots; 1 PXI Express system timing slot; 1 system slot
- Up to 24 GB/s system Bandwidth (each direction)
- Up to 8 GB/s slot bandwidth (each direction)
- Removable power shuttle; 925 W total system power
- 38.25 W power and cooling capability per slot
- Optional rack mount kit
See the Resources section of the PXIe-1085 24 GB/s model page for full user manual and specifications
Figure 4. Front view of a vacant PXIe-1085 24 GB/s chassis.
PXI Express Specification
As the complexity of customer applications and demand for processing power and bandwidth have grown over the past decades, the PXI specification has evolved to meet these needs. Initially PXI was based on PCI technology and provided 132 MB/s of data bandwidth. This specification then evolved into PXI Express by leveraging PCI Express technology, which sends data serially through pairs of transmit and receive connections called lanes, which give data the ability transfer at 250 MB/s per direction with PCI Express Gen 1 technology. Multiple lanes are grouped together to form x4, x8 and x16 links to increase bandwidth.
This then grew to 500 MB/s per lane with PCI Express Gen 2 technology. With the release of the PXIe-1085 24 GB/s chassis, the industry’s first chassis that is based on PCI Express Gen 3 technology, the lane bandwidth has been doubled to 1 GB/s per lane, and with 24 data lanes (x24), a total of 24 GB/s of data per direction can be sent from the controller to the PXI Express backplane as seen in Chart 3 below.
It is important to note that the system bandwidth outlined in the previous paragraph addresses only the amount of data that can be transferred between the system controller and the chassis. When utilizing peer-to-peer (P2P) communication between peripheral modules, the total amount of data that can be transferred in the chassis increases dramatically. As an example, three peripheral modules streaming to system controller at 8 GB/s and seven pairs of modules utilizing P2P at 8GB/s, in theory, total system bandwidth becomes 80 GB/s in single direction and 160 GB/s bi-directionally. Actual system bandwidth will vary based on many factors such as memory bandwidth, PCIe packet sizes and overhead, single vs. bidirectional traffic, etc.
Chart 3. System bandwidth for each generation of PXI and PXI Express
based on the 24 available data lanes (x24).
All Hybrid Slots
Along with advancements in chassis communication buses to incorporate the latest PC technology, PXI peripheral modules have evolved from PXI to PXI Express to take advantage of PCI Express communication bus capabilities. To ensure module compatibility between PXI and PXI Express modules, the PXI specification added the hybrid slot. With this slot, you can insert hybrid-compatible PXI or PXI Express peripheral modules in PXI chassis and leverage any previous investments in hybrid-compatible PXI modules. As with the previous 12 GB/s PXIe-1085 chassis, the 24 GB/s variant is an 18-slot chassis (one system controller + 17 peripheral slots) with 16 hybrid slots.
PXI Backplane Technology
A key benefit of the PXI platform over traditional instrumentation is the integration of triggering, power, reference clocks, and data buses, which normally require external cables, into the PXI chassis backplane. For the PXIe-1085 24 GB/s chassis based on PCI Express Gen 3 technology, the key innovation is the implementation of two Gen 3 switches as seen in Figure 5. These switches handle the routing of information from module to module and between the modules and controllers.
Figure 5. Rear view of the PXIe-1085 24 GB/s chassis with the power shuttle
removed to view the PCI Express Gen 3 switching technology.