# High-Speed Digital I/O Logic Families

Publish Date: Jun 03, 2014 | 6 Ratings | 4.00 out of 5 | Print

## Overview

This tutorial is part of the National Instruments Measurement Fundamentals series. Each tutorial in this series, will teach you a specific topic of common measurement applications, by explaining the theory and giving practical examples. This tutorial covers the common types of digital logic families.

You can also view an interactive presentation (10min video) that takes you through this tutorial's material at your own pace.

For additional digital only concepts, refer to the Digital I/O Fundamentals Main page.
For the complete list of tutorials, return to the NI Measurement Fundamentals Main page.

### 1. Overview of the Logic Families

Logic families are groups of logic circuits with standardized voltage levels that constitute a voltage high or low level. All circuits within a logic family are compatible with other circuits within that family, since they share the same characteristics.

### 2. Single-Ended Logic Families

Single-ended logic families use standardized single-ended voltage levels to interpret the voltage swing between the voltage driven by the device and
ground as either a one or a zero. Examples of the voltage levels for common single-ended logic families are shown in table 1.

 Logic Family Voltage Range CMOS 0 to 5 V TTL 0 to 5 V LVTTL 0 to 3.3 V LVCMOS 0 to 3.3 V
Table 1. Common Signal-ended Logic Families

Visit the High-Speed Digital I/O Voltage Levels tutorial to learn about the different voltage parameters.

### 3. Differential Logic Families

Differential logic families use differential voltage levels to measure the voltage difference between a pair of wires.

Low-Voltage Differential Signaling (LVDS)
Low-voltage differential signaling (LVDS) is a low-noise, low-power, low-amplitude differential method for high-speed digital data transfer.

Figure 1: Diagram of the typical LVDS circuit

As you can see in the previous figure, a current source at the driver provides approximately 3.5 mA of current. The direction of the current across the transmission line depends on whether the driver drives a logic high level or low level. When the current reaches the receiver, a 100 Ω terminating resistor connects the two ends of the differential transmission line to provide a return path for the current. A voltage of approximately 350 mV (3.5 mA x 100 Ω) is established across the two input terminals of the receiver. The differential voltage at the receiver is either positive or negative, depending on the direction of the current. The receiver recognizes a positive differential voltage signal as a logic high level (1) and a negative differential voltage as a logic low level (0). The electrical characteristics of an LVDS signal offers many performance improvements compared to single-ended standards.

For example, since the received voltage is a differential between two signals, the voltage swing between the logic high level and low level state can be smaller, allowing for faster rise and fall times and thus faster toggle and data rates. Also, as with LVPECL circuits, the differential receiver is less susceptible to common-mode noise than single-ended transmission methods.

The LVDS standard defines the electrical aspects of this type of data transmission. The standard defines driver and receiver electrical characteristics only. The standard does not create protocol, interconnect, or connector definitions because these aspects are application specific.

Note: Refer to the ANSI/TIA/EIA-644-A electrical characteristics standard, Electrical Characteristics of Low-Voltage Differential Signaling (LVDS) Interface Circuits, Revision A, 2001 edition for more information.

Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Emitter-Coupled Logic circuits use a design that uses transistors to steer current through gates which compute logical functions. Because the transistors are always in the active region, they can change state very rapidly, so ECL circuits can operate at very high speeds. LVPECL circuits are a type of ECL circuit that require a pair of signal lines for each channel. The differential transmission scheme is less susceptible to common-mode noise than single-ended transmission methods. LVPECL circuits are designed for use with VCC = 3 V or 3.3 V.

Visit the High-Speed Digital I/O Voltage Levels tutorial to learn about the different voltage parameters.

To learn how to interface with ECL devices with NI digital I/O devices.

### 4. Relevant NI Products

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For the complete list of tutorials, return to the NI Measurement Fundamentals Main page

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