1. New LabVIEW 2012 Features
Proven, NI Recommended Architectures for Control and Monitoring Applications
For LabVIEW applications based on NI CompactRIO / Single-Board RIO hardware, the new LabVIEW Project Templates and Sample Projects provide applications and source code that are designed to scale to a wide variety of control and monitoring applications.
Figure 1. LabVIEW 2012 Sample Projects provide proven, reliable architecture starting points for embedded control and monitoring applications
If you’re starting a new application, the Sample Projects provide a starting point that can shorten your development time and ensure that your design is reliable. If you have an existing LabVIEW RIO application that you would like to optimize or improve, you can leverage the Sample Projects to learn LabVIEW FPGA design techniques and architectural best practices that are specific to embedded applications. For more information on LabVIEW Sample Projects for control and monitoring applications, see the LabVIEW Real-Time 2012 Sample Projects Webcast and the LabVIEW Templates and Sample Projects whitepaper.
Better Verification of FPGA VI With Execution on Development Computer
Compiling an FPGA VI can take minutes to hours. However, you can test the logic of an FPGA VI before compiling it by running the FPGA VI on a development computer with simulated I/O. When you run the FPGA VI on the development computer, you can use all traditional LabVIEW debugging techniques, such as probes, execution highlighting, breakpoints, and single-stepping. In LabVIEW FPGA 2012, when you run your FPGA VI on your development PC, you will notice improved fidelity with respect to time when executing multiple Single-Cycle Timed Loops at same or different clock rates, and when sharing resources between two or more Single-Cycle Timed Loops.
Figure 2. Improved fidelity when executing FPGA VI on development computer
Floating-Point Support Within LabVIEW FPGA
Previous versions of LabVIEW FPGA required developers to use the fixed-point data type when fractional data was needed. While the fixed-point data type is very efficient for hardware-based designs when it comes to speed and resource utilization, it does not provide the flexibility that the floating-point data type offers. In LabVIEW FPGA 2012, the single-precision floating-point data type is natively supported. Not only will this enable users to directly retrieve floating-point data from DMA FIFOs, avoiding an expensive conversion from fixed-point to floating-point on the real-time or windows host, but it will enable DSP designers to solve linear-algebra problems in LabVIEW FPGA that require a wider dynamic range that what fixed-point or integer type data provide. It is important to note that while the floating-point data type offers many benefits, it has limited support when used in Single-Cycle Timed Loops, and uses significantly more FPGA resources than the fixed-point data type for certain operations.
Figure 3. Floating point data type support in LabVIEW FPGA 2012
For more information on the functions and structures that support the floating point datatype, see the LabVIEW FPGA 2012 Help document Functions that Support the Single Precision Floating-Point Data Type in FPGA VIs. For benchmarks that compare floating-point datatype resource utilization to fixed-point, see the whitepaper LabVIEW FPGA Floating Point Data Type Support.
Array and Cluster Support Within Single-Cycle Timed Loops
In LabVIEW FPGA 2012, boolean, numeric, and comparison operations within single-cycle timed loops now support cluster and array data types. Each primitive operation is parallelized on the FPGA for maximum performance, so you no longer need to break out each operation individually. This idea was originated from the LabVIEW FPGA Idea Exchange.
Figure 4. Cluster and array data type support added to single-cycle timed loops
Faster Compilations With Support for Linux
When it’s time to compile your LabVIEW FPGA VI, you can iterate faster with new Linux-based FPGA compilation options. Linux-based compilation workers offer substantial performance benefits over Windows-based workers. For large, complex FPGA VIs, NI has seen a significant decrease in compilation times. The performance gains vary based on the specifications of the machine performing the compilation and the size of the FPGA target. Linux-based compilation is available with the LabVIEW FPGA Compile Compile Cloud Service, in addition to remote PC compile works and the NI Compile Farm Toolkit. For more information on using Linux machines as a compile worker with LabVIEW FPGA 2012, see the NI LabVIEW FPGA Compilation Options whitepaper and the FPGA Compile Worker Performance Benchmarks whitepaper.
Figure 5. Linux-Based FPGA Compilation Options
Higher Clock Rates with Single Cycle Timed Loops
In order to compile Single-Cycle Timed Loops at higher clock rates for very large streaming applications, the compiler, under certain conditions, can remove enable chain for the Single-Cycle Timed Loops that have no dataflow dependences. Removing this enable chain will decrease routing congestion and improve timing performance. For more information on how to leverage this new feature, see the LabVIEW FPGA 2012 Help document Improving Timing Performance in Large FPGA VIs.
Array Support with High-Throughput Math Nodes
When designing sophisticated DSP algorithms for high-throughput applications, there is often a need to perform high-throughput math on arrays. In LabVIEW FPGA 2012, the High-Throughput Math Nodes support fixed-size array inputs, eliminating the need to perform math operations element-by-element with multiple nodes.
Figure 6. Array Support for High-Throughput Math Functions
New Tools for Simplifying IP Reuse
When designing LabVIEW FPGA algorithms, it’s important to be able to re-use the IP that was created for one application within another. Often times, developers find themselves modifying the algorithm they created, so that they FPGA VI will compile in a way that it meets system requirements, such as execution speed, throughput, or latency. When they want to reuse this algorithm for another application with different system requirements, they are required to make major modifications to the LabVIEW FPGA source code. LabVIEW FPGA IP Builder is an add-on tool to LabVIEW FPGA , that enables developers to write one algorithm that can be easily compiled for multiple systems for various system requirements, without modifying the source code. For more information on LabVIEW FPGA IP Builder, see the whitepaper Get Better Performance and Resource Utilization with LabVIEW FPGA IP Builder.
Figure7. LabVIEW FPGA IP Builder enables users to design an algorithm in LabVIEW, and compile it for multiple applications with different performance requirements
FIFO Improvements for Faster Streaming
LabVIEW FPGA 2012 includes several new features that enable improved streaming performance with FIFOs for PXIe FlexRIO targets. One example is a deeper and wider DMA FIFO. The depth of a DMA FIFO has been increased from 32k samples to 256k samples, making it easier to achieve sustainable rates when streaming data at very high rates.
Additional improvements to both the DMA FIFO and Peer-to-Peer FIFO enable users to pack small data sizes elements into a 64-bit array before sending to a host. With this new feature users can obtain higher transfer rates when transferring smaller data size elements between an FPGA target and host. The number of elements that can be sent with a FIFO will depend on the datatype of the elements.
Figure 8. Write four 16-bit integers in parallel with DMA and Peer-to-Peer FIFOs for PXIe FlexRIO Targets
Improved Ability to Create Reusable SubVIs
You now have the option to use a new LabVIEW FPGA construct, the Register, to write light-weight, re-usable code for communication between loops executing in parallel. You can think of the Register as a single-element Memory implemented with flip-flops. Like globals, you can write and read Registers in the same or different clock domains. Similar to FPGA I/O, Memories, FIFOs, and Clocks, Registers can be specified via name controls, which is how you write reusable subVIs with Registers.
Figure 9. Register functions are consistent with those for Memories and FIFOs
For more information on creating reusable subVIs with LabVIEW FPGA, see the NI LabVIEW FPGA 2012 Help Document Using Register Items in SubVIs. For more information on the Register, see the NI LabVIEW FPGA Help Document Register Items.
2. New LabVIEW 2011 Features
More Efficient Development
With the NI LabVIEW 2011 FPGA Module, you can now develop your custom logic and Host VI Interface code quicker and more efficiently than ever before. After thoroughly analyzing the common edit-time operations performed during development, NI concentrated on optimizing time-intensive operations – from manipulating Host Interface functions to opening and closing field-programmable gate array (FPGA) VIs.
Figure 10. The LabVIEW 2011 FPGA Module contains optimizations that help you develop your custom logic faster by reducing the time required for common edit-time operations.
Simplified Xilinx CORE Generator IP Access
You can now drag and drop configurable Xilinx CORE Generator IP blocks directly from the LabVIEW FPGA palette onto the block diagram. This streamlines integrating existing communications, math, and even image or video processing IP using the same IP Integration Node introduced in the LabVIEW 2010 FPGA Module.
Figure 11. With the new Xilinx CORE Generator IP palette, you have easier access to existing FPGA IP that you can use to accelerate your development process.
Expanded Options for Cycle-Accurate Simulation
In addition to executing cycle-accurate LabVIEW FPGA application simulations with the Mentor Graphics ModelSim tool, you can now use the Xilinx iSim environment included with the LabVIEW 2011 FPGA Module. Furthermore, when working with ModelSim simulations, you can now use LabVIEW to quickly create test benches that use cosimulation to validate logic signal propagation, rather than working directly with HDL.
3. New LabVIEW 2010 Features
IP Integration Node
The IP Integration Node replaces the HDL Interface Node as a way to bring in third-party IP. Point the node to existing VHDL or use the built-in compatibility with the Xilinx Core Generator. This node also automatically creates a simulation model for the IP. Because of this, you can simulate the FPGA diagram on the development computer even if they have CoreGen or straight VHDL. Once you have configured the node, you can use the IP just like any other LabVIEW node with inputs and outputs.
New Compilation Features with Compile Farm/Cloud Software and Build Specifications
LabVIEW FPGA now uses build specifications to hold properties of compilations for a particular VI. This helps you organize your compiles and easily experiment with different Xilinx tool configurations. NI also released a toolkit that you can use to create a multimachine compile farm to offload FPGA compiles from their development machines. NI is experimenting with incorporating this technology in the cloud as well. The LabVIEW FPGA Cloud Compile Service, a beta feature for LabVIEW 2010, helps you easily use high-end dedicated machines for lengthy FPGA compilations.
Cycle-Accurate Simulation with ModelSim
LabVIEW 2010 can export the LabVIEW diagram to a set of files that you can analyze in off-the-shelf simulation software. Using these methods, you can run cycle-accurate simulations of your LabVIEW FPGA system. Keep in mind that this feature is for those who have experience with ModelSim and other FPGA design tools.
New and Improved IP
LabVIEW 2010 also features new FPGA IP for statistics, such as mean, variance, and standard deviation; a new complex multiply; a matrix-vector multiply; and a complete implementation for the DSP48E MAC block. New memory IP includes a dual-port read and external DRAM support. Finally, there are CLIP improvements including a configuration wizard to replace XML creation and VHDL generic support.
Dynamic Host Interface Wire
Previously, the FPGA interface was difficult to reuse because the FPGA reference wire was strictly typed to the bitfile or VI. As of LabVIEW 2010, NI has created a dynamic reference wire that you can apply to more easily reuse subVIs you build with FPGA interface VIs. Keep in mind that the FPGA VI still features a name-based connection to the registers (front panel controls and indicators). You need to make sure these names are also reusable when using this feature. In addition, you can use the legacy strictly typed wire if needed moving forward.
4. New LabVIEW 2009 Features
Early Size and Speed Resource Estimation
A large portion of user feedback asked for more estimation of the FPGA resource usage before waiting through an entire compile. With LabVIEW 2009, the compiler shows early size and speed estimates of your design after the “synthesis” step and alerts you when this report is ready for viewing.
Timing Violation Debugging with Critical-Path Highlighting
When a timing violation occurs, often called “not meeting timing,” it can be difficult to diagnose the critical path and reduce the timing constraints by programming more efficiently and adding pipeline stages. Now, timing violations give you a window that shows every VI in the critical path and highlights the location of the VI on the FPGA block diagram. The feature even examines subVIs to discover the source of a timing violation.
New and Improved High-Throughput Math and Signal Processing IP
New high-throughput math VIs offer new functions, such as sin, cos, and exponential, with the high-speed handshaking protocol that allows the functions to be used in a single-cycle Timed Loop. You not only have new math functions, but you can use them with other functions in a high-throughput signal chain such as Window, FFT, and resample.
Host Integration Features
On the host side, there are two important features in LabVIEW 2009. First, NI has exported a C Interface so that you can talk to your LabVIEW FPGA program running in hardware with C. The functionality includes read/write registers, DMA, and interrupts. Second, LabVIEW 2009 features new scaling companion VIs for certain FPGA IP functions. For example, there is a VI that converts the raw FFT data to a spectrum; a VI that prepares coefficients for FPGA filtering VIs; and a VI that takes frequency, amplitude, and phase and returns values to use with signal generation VIs.
5. New LabVIEW 8.6 Features
Enhanced Behavioral Simulation
For more efficient development, you can use enhanced behavioral simulation to run the code on the development computer and verify functionality before compilation. Additionally, in LabVIEW 8.6, you can use LabVIEW programs that assert test vectors or interactive values to the input I/O nodes in the field-programmable gate array (FPGA). Capture the outputs for verification and visualization of FPGA behavior, run the host at the same time as the FPGA on the development computer, and get simulated register and DMA transfers between the simulated FPGA and host code. With these new features, you can create a test bench for the FPGA code and simulate the entire system without always compiling to check logic.
FFT and Other New IP
In LabVIEW 8.6, you can implement FFT with windowing on the FPGA. This is one of the most requested features, and NI has delivered a customizable IP core that can execute FFT, inverse FFT, multiple bin sizes, and multiple throughput settings. NI also released rational resampling, divide, square root, adaptive filters, and fixed-point overflow handling functions.
The fixed-point data type is now supported on nearly every FPGA function input. This includes support for DMA, memory, filters, PID, FFT, and all arithmetic. Additionally, the fixed-point data type offers an option to add an overflow bit carried on the wire. NI will continue to enhance fixed-point support in the future to work with resource-constrained targets.
Component-Level IP (CLIP)
CLIP is a new way to import and use external IP written in a hardware description language (HDL). Implementations instantiated with CLIP run in parallel with the LabVIEW diagram, and you communicate to them through user-created I/O nodes. With some hardware targets, you can use CLIP to talk directly to I/O pins. CLIP functions open the FPGA platform further to include all types of IP, which may be better suited to run in parallel rather than in data flow like the current HDL Interface Node runs.
6. New LabVIEW 8.5 Features
FPGA Project Wizard
The new FPGA Project Wizard helps you create a complete LabVIEW project with the FPGA target and I/O configured and ready to program. Because it can directly link to the existing FPGA Wizard, you can quickly generate functional code for analog and digital I/O, counter, and quadrature encoder measurements. The FPGA Project Wizard is enhanced with new DMA options for FPGA and host code generation.
Control, Filtering, and Signal Generation IP
The LabVIEW FPGA Module 8.5 includes new IP in the FPGA palette as well as enhanced existing IP for improved resource use on the FPGA.
- Control – Included in the LabVIEW PID and Fuzzy Logic Toolkit, the proportional integral derivative (PID) block in FPGA now works with multiple channels, so you can input an array of channels into the same PID logic on the FPGA. This enhancement is especially important for high-channel-count applications. The number of possible channels rose from 8 to 256 for a 1M gate target. Additionally, the single-channel benchmark is three times faster and uses almost 20 percent fewer FPGA resources.
- Filtering – All filters are also compatible with multiple channels. Additionally, LabVIEW FPGA includes a new notch filter, rounding out the existing Butterworth highpass and lowpass filters.
- Signal generation – In addition to the existing sine generator, LabVIEW FPGA now features a square wave generator and noise generators (Gaussian and white).
Modularity and Code Reuse Features
- I/O name controls – Put I/O nodes, methods, and properties inside subVIs to specify the I/O item through a wire.
- Clock controls – Use a wire to specify which clock, such as an onboard or derived clock, to use in a particular single-cycle Timed Loop.
- Enhanced feedback node – Place a feedback node anywhere in a block diagram to escape the context of a loop. Feedback nodes can be useful for state storage or pipelining and now work anywhere, including subVIs.
LabVIEW Statechart Module
NI now offers additional ways to program FPGAs graphically. Many designers prefer using statecharts to represent the system they want to build. With this new module supporting LabVIEW FPGA, designers can not only represent FPGA-based systems with statecharts but also program them with the same visual paradigm.
Pioneer-Level Support for Fixed-Point Data Type
There is a new fixed-point data type in LabVIEW that is especially useful for FPGA programming. Previously, LabVIEW FPGA supported only integers. However, with support for new fixed-point data types, you can bring fractional numbers and arbitrary bit-width data types to FPGA programming. LabVIEW 8.5 features fixed-point support for a small number of primitive math and comparison functions. Future releases may expand support for this important data type.
7. New LabVIEW 8.2 Features
FPGA Math and Analysis IP
The LabVIEW FPGA Module 8.2 provides new native analysis functions so you can reuse code for basic signal processing and control functionalities common to FPGAs. This new IP includes:
- Direct current (DC) and root-mean-square (RMS) measurements - calculates the DC, RMS, sum, mean square, and/or square sum values of a signal
- Butterworth filter - filters an input signal using a Butterworth filter that is configurable using this Express VI
Period measurement - calculates the period of an evenly sampled periodic signal using threshold crossing detection
You can design FPGA I/O and timing for your intelligent data acquisition applications with the FPGA Wizard. Using this configuration-based wizard, you can select the timing and synchronization between your FPGA device and host VI. After selecting your timing, you can configure your analog, digital, counter, or quadrature encoder I/O. Once you have configured your I/O, you can save your configuration and generate basic FPGA code and host code. You can then incorporate additional code to complete your application functions such as control algorithms, data logging, or data networking.
New Memory VIs
With the new memory read and write interface, you can access all 80 KB of memory on 1M gate devices and all 190 KB of memory on 3M gate devices. You can use memory to store data for waveform generation or data logging without using arrays that inefficiently use FPGA gates.
8. New LabVIEW 8.0 Features
With a LabVIEW project, you not only can target and open VIs in LabVIEW for Windows, the LabVIEW FPGA Module, the LabVIEW Real-Time Module, and other LabVIEW modules simultaneously but also develop LabVIEW FPGA applications. As seen below, you can use a LabVIEW project to create and manage all FPGA resources, including:
- FPGA I/O
- Custom clocks
- CompactRIO configurations
- FPGA FIFOs
DMA Data Transfers
The LabVIEW FPGA Module 8.0 DMA capabilities eliminate throughput limitations between the FPGA device and host. While FPGAs on reconfigurable I/O (RIO) devices can run at rates up to 20 MHz, the fastest data-streaming rate without DMA is approximately 1 MB/s. The LabVIEW FPGA Module 8.0 implements DMA on all National Instruments R Series and CompactRIO devices for at least a 20 times increase in data-streaming rates between the FPGA and a host application compared to other implementations such as using interrupt requests.
DMA provides a direct data-to-RAM link on the host machine. Relying on the host processor to stream data from the device to the host often leads to latencies and causes a data transfer bottleneck. Using interrupt requests also consumes processor clock cycles and increases the overall load on a host CPU. With LabVIEW 8, you gain more efficient device-to-host and host-to-device data transfers that bypass the CPU, creating a higher-performance data acquisition system for all applications.
To use DMA, simply create two memory buffers – one in memory on the FPGA device and one in memory on the host processor – and LabVIEW efficiently and transparently transfers data over the PCI bus. The LabVIEW FPGA Module 8.0 uses FPGA FIFOs configured for DMA to write and read to DMA memory and uses FPGA invoke methods on the host side to create, write, and read from host memory. DMA significantly enhances RIO hardware for applications such as buffered intelligent data acquisition, communication device digital streaming, in-vehicle data acquisition, and online machine condition monitoring.
Drag-and-Drop FPGA I/O
With LabVIEW FPGA, you quickly can access RIO device I/O through specific device I/O functions. (However, the LabVIEW FPGA function palettes mentioned in this document are specific to FPGA execution targets and contain functions available only when targeted to an FPGA device or FPGA device emulator.) The LabVIEW FPGA Module gives you direct single-point access to analog and digital I/O on NI RIO hardware. With the LabVIEW FPGA Module 8.0, you can directly drag and drop I/O from the LabVIEW project window onto the block diagram of your FPGA VI.
The LabVIEW FPGA Module offers many device I/O functions, including:
- Analog input
- Analog output
- Digital input
- Digital output
- Digital port input
- Digital port output
- I/O Method Node
- I/O Property Node
9. New LabVIEW 7.1 Features
Single-Cycle Timed Loop
The LabVIEW Timed-Loop structure executes a loop at the period you specify. Use the Timed Loop to develop VIs with multirate timing capabilities, precise timing, and feedback generation on loop execution or to dynamically change timing characteristics or several execution priority levels. Read a tutorial for more information on the Timed Loop. The LabVIEW FPGA single-cycle Timed Loop is a specialized Timed Loop with which you can develop LabVIEW FPGA applications as efficiently (in terms of speed and space) as hand-coded HDL programming. The single-cycle Timed Loop is similar to a clocked process in VHDL. All of the LabVIEW code in the loop is combinatorial logic on the FPGA, where inputs are from components such as digital input functions, controls, or left-shift registers and outputs are digital output functions, indicators, and right-shift registers. It is easy to take advantage of a single-cycle Timed Loop – use it as you do a standard While Loop.
The single-cycle Timed Loop ensures that all code within the loop executes in a single clock cycle (25 ns). While there are some limitations to the single-cycle Timed Loop, such as ensuring that all the code inside it can execute within a clock cycle, using it can result in extremely efficient code for executing digital I/O and simple logic and signal processing. Learn about the single-cycle Timed Loop functions and I/O nodes in LabVIEW FPGA.
HDL Interface Node
You can integrate existing HDL IP directly into a LabVIEW FPGA VI using the HDL Interface Node and represent this code as a single function block within LabVIEW. You then can reuse this code within the same application or in other applications using the same function block. If you have a block of HDL code to use in an FPGA VI, you can either enter your VHDL code directly into the HDL Interface Node or refer to external .vhd files rather than rewriting the code in LabVIEW.
10. Next Steps