1. New LabVIEW 2015 Features
Using IP on the LabVIEW Tools Network to Establish Master‑Slave Communication
The LabVIEW 2015 FPGA Module includes the new Communication Protocols functions for you to access communication protocols IP available on the LabVIEW Tools Network at ni.com/labview-tools-network. You can use the IP to establish master‑slave communication in an FPGA application through communication protocols, such as Inter-Integrated Circuit (I2C) and Serial Peripheral Interface (SPI).
You can use the new Flush method to flush data from a DMA target-to-host FIFO to the host or from a peer-to-peer writer FIFO to the peer-to-peer reader FIFO. The Flush method minimizes latency in data transfers because this method requires LabVIEW to transfer any data in a FIFO as soon as possible. Without the Flush method, LabVIEW transfers data in a FIFO only when the amount of data in the FIFO reaches a threshold or an internal timer in the FPGA expires. Use the Flush method only when low latency is important to you. Excessive use of the Flush method might reduce data transfer rates. Use the FIFO Method Node to implement this method.
Implementing a Floating-Point PID Algorithm
The LabVIEW 2015 FPGA Module provides the following new VIs for you to implement a floating-point Proportional-Integral-Derivative (PID) algorithm on FPGA targets:
PID VI—Use the PID VI to implement a single-precision floating-point PID algorithm for PID applications with high-speed control and/or high channel count on an FPGA target. The PID VI is located on the Control palette.
Convert PID Gains VI—Use the Convert PID Gains VI to convert PID gains in the Academic, Parallel, or Series form to the normalized Parallel form that the PID VI expects. The Convert PID Gains VI is located on the Scaling palette.
New Example VIs for the FPGA Desktop Execution Node
The LabVIEW 2015 FPGA Module includes the following new example VIs that use the FPGA Desktop Execution Node to simulate analog and digital signals:
Simulating Analog Signals with the DEN
Simulating Digital Signals with the DEN
Use the NI Example Finder, available by selecting Help»Find Examples from LabVIEW, to access the new example VIs. For detailed information about these examples, refer to the readme.html file in each example.
Figure 1. The new FPGA Desktop Execution Node examples show you how to simulate your FPGA VI and test inputs and outputs before compiling.
2. New LabVIEW 2014 Features
LabVIEW FPGA Compile Cloud Service for NI Standard Service Program (SSP) Members
The LabVIEW FPGA Compile Cloud Service is now included in the LabVIEW FPGA Module for customers who have an active NI Standard Service Program (SSP) membership. The LabVIEW FPGA Compile Cloud Service gives you the ability to offload your LabVIEW FPGA compilations to high-performance, Linux-based servers in the cloud. It includes the following benefits:
-Offers up to 30% reduction in compile times for NI CompactRIO targets, and up to 60% reduction in compile times for NI FlexRIO and vector signal transceiver (VST) targets
-Provides the ability to execute multiple compilations in parallel
-Frees up development machine resources
-Provides the ability to shut down the development machine at any time during a compile
-Saves hard drive space if you choose to not install the Xilinx compilation tools locally (see the support document titled When Do I Need to Install the Xilinx Compilation Tools?)
In addition, the LabVIEW FPGA Compile Cloud Service requires zero on-site installation and maintenance. To start using this free service today, visit ni.com/trycompilecloud.
LabVIEW FPGA Compile Farm Toolkit
The LabVIEW FPGA Compile Farm Toolkit is now included in the LabVIEW FPGA Module. If you prefer to offload LabVIEW FPGA compilations to a farm of on-site workers versus sending them to the cloud, the LabVIEW FPGA Compile Farm Toolkit provides software to create an on-site server to manage FPGA compilations. You can connect as many worker computers as you need, and the central server software manages the farming out of parallel compilations and queuing. To reduce your FPGA compile times, the toolkit also includes support for Linux compile worker computers.
LabVIEW FPGA IP Builder
LabVIEW FPGA IP Builder is now included within the LabVIEW FPGA Module. LabVIEW FPGA IP Builder generates high-performance FPGA IP by combining high-level synthesis technology with the power of LabVIEW. You can use LabVIEW FPGA IP Builder to:
For more information on LabVIEW FPGA IP Builder, see Using NI LabVIEW FPGA IP Builder to Optimize and Port VIs for Use on FPGAs.
LabVIEW FPGA IP Builder Improvements
The LabVIEW 2014 FPGA IP Builder includes new programming elements so you can create portable algorithms. New features include:
-Deferred Size Check for Arrays: Arrays can have variable sizes as long as the size can be determined at code generation. This makes it possible to create reusable subVIs that implement your algorithms. You can use the same subVI in different applications.
Figure 1. Arrays that are used in the IP Builder context can have variable sizes.
-Additional Tunnel Modes:
-Concatenating tunnels enable IP creation for processing multidimensional arrays. LabVIEW FPGA IP Builder (and LabVIEW FPGA) does not support multidimensional arrays. However, multidimensional arrays can be serialized and processed by your IP. Concatenating tunnels enable reassembling of multidimensional arrays.
-Conditional tunnels are useful for multirate algorithms like decimation, where the number of elements at the output is different from elements at the input.
Figure 2. Additional tunnel modes are supported within the IP Builder context in the LabVIEW 2014 FPGA Module.
-Conditional Disable Structure: This feature makes it possible to create portable algorithms that you can run on the desktop or in the IP Builder context.
Figure 3. The conditional disable structure can detect whether your code is executing in the Windows context or in the IP Builder context.
New Vision IP for LabVIEW FPGA
The NI Vision Development Module 2014 includes over 50 image-processing functions that can be offloaded to the FPGA for maximum processing performance, in addition to an API to pass images between the CPU and FPGA. For quick prototyping, you can use the Vision Assistant to automatically generate the LabVIEW Project and VIs for the FPGA, host CPU, and the interface between the two targets. You can modify the new vision IP through the LabVIEW FPGA IP Builder.
Figure 4. Offload new vision IP to FPGA hardware for maximum processing performance.
LabVIEW PID Toolkit
The LabVIEW PID Toolkit functionality for FPGA targets is now included in the LabVIEW FPGA Module. Use the LabVIEW PID Toolkit to implement single or multichannel proportional integral derivative (PID) control algorithms in LabVIEW FPGA. The included PID (FPGA) Express VI implements a fixed-point PID algorithm. A floating-point implementation of this same PID algorithm is included in the white paper titled Floating-Point Implementation of a LabVIEW FPGA PID Controller.
Figure 5. The latest version of LabVIEW FPGA includes a single or multichannel PID control algorithm.
Xilinx Vivado Support for Kintex-7 LabVIEW FPGA Targets
The new Kintex-7 FPGA and Zynq system on a chip (SoC) from Xilinx offer a perfect balance of FPGA fabric clock rate performance, low power, high-speed I/O, capacity, security, and reliability. In LabVIEW 2014, developers using Kintex-7 FPGAs or Zynq SoCs in their NI RIO hardware can also benefit from the latest compilation technology from Xilinx. The new Xilinx Vivado compilation tools offer several benefits including:
-More reliable, consistent timing closures
-Improved resource utilization
-Faster compiles for Kintex-7 FPGA and Zynq SoC targets previously using Xilinx ISE (NI cRIO-9068 and NI PXIe-7975R)
Figure 6. Xilinx Vivado offers reduced compilation times for Kintex-7 and Zynq SoC targets
For a list of all NI RIO hardware that uses Kintex-7 FPGAs, see the support article titled Which Xilinx FPGA Chips Are Used by National Instruments RIO Devices?
4-Wire Handshaking API for FIFOs
Four-wire handshaking is commonly used in high-throughput streaming applications. First-in-first-out memory buffers (FIFOs) are commonly used to transport data between processing elements within these applications. The new 4-wire handshake interface on FIFOs gives you the ability to easily integrate them in high-throughput designs.
Figure 7. Use a 4-Wire Handshaking API for FIFOs that you can easily integrate into high-throughput streaming applications.
Higher Performance BRAM
Xilinx Block RAM has optional registers at the output. By enabling these registers, you can effectively pipeline the memory and break up the critical path, and synthesize their design at a higher clock rate. It is important to note that enabling the registers adds latency to the memory access, and you need to add feedback nodes equal to or greater than the cycles of latency configured.
Figure 8. Take advantage of high-performance BRAM to synthesize your design at a higher clock rate.
3. New LabVIEW 2013 Features
FPGA High-Performance Linear Algebra Library
Advanced applications such as radio frequency communications, image and audio processing, heat distribution, and cryptography require high-performance algorithms on reconfigurable hardware. The LabVIEW 2013 FPGA Module includes new IP libraries that give you the ability to implement FPGA-based high-performance algorithms.
Building basic linear algebra operations with specific timing, resource utilization, and throughput requirements in FPGAs can be a challenge. To alleviate this challenge, the LabVIEW 2013 FPGA Module introduces a new IP library that includes the most common linear algebra functions: matrix transpose, dot product, vector norm square, and matrix multiply.
Figure 1. The LabVIEW 2013 FPGA Module includes a new IP library that features the most common linear algebra operations.
These operations serve as basic building blocks for many numerical linear algebra applications, including the solution of linear systems of equations, linear least square problems, eigenvalue problems, and singular value problems.
Figure 2. The linear algebra library helps you meet your requirements on timing, resources, and throughput.
Instrument Driver FPGA Extensions
Test engineers now have even more options for programming their software-designed instruments such as NI vector signal transceivers (VSTs) with the release of instrument driver FPGA extensions. This feature combines the compatibility of the full-featured NI-RFSA and NI-RFSG instrument drivers with the flexibility of the completely open-source LabVIEW sample projects and instrument design libraries. You can add application-specific IP to your VST FPGA while preserving all of the features of the NI-RFSA and NI-RFSG instrument drivers, and without modifying those APIs. Potential FPGA enhancements include custom and/or novel instrument capabilities such as frequency mask triggering, better system integration through hardware-timed device under test (DUT) control and the deterministic triggering of other instruments, accelerated test throughput with FPGA-based measurement acceleration and coprocessing, and even closed-loop or “protocol-aware” tests in which the instrumentation hardware responds to the DUT in real time.
Figure 3. Instrument driver FPGA extensions give you the ability to define custom capabilities for software-designed instruments, while preserving instrument driver functionality and APIs.
Improved Signal Visualization in Debugging Tools
You can use traditional debugging tools such as probes, execution highlighting, breakpoints, and single-stepping when simulating your FPGA VIs on the development computer. However, in FPGA designs that involve communication protocols, you need to view signals in relation to each other with history data in order to debug the application. The LabVIEW 2013 FPGA Module introduces a new probe based on sampling events that makes it easy to visualize signals on a waveform graph, including relevant timing information.
Figure 4. The Sampling Waveform Probe gives you the ability to visualize multiple signals on a waveform graph based on sampling events.
The Sampling Waveform Probe can use While Loops, For Loops, and FPGA clock domains as sampling event sources. Multiple wires on the block diagram can be associated to those sampling sources so they can be visualized together on the Sampling Probe Watch Window. This new way of visualization makes it easier to analyze multiple signals, especially when they are generated within a single-cycle Timed Loop.
Extended I/O Simulation and Timing Control Capabilities
LabVIEW FPGA gives you the ability to generate I/O signals to simulate the functionality of real-world I/O. This is traditionally done by simulating random data or configuring a custom simulation VI. The LabVIEW 2013 FPGA Module offers a more direct path for providing simulated data to your LabVIEW FPGA VI.
Figure 5. The FPGA Desktop Execution Node facilitates the simulation of FPGA VIs in the development environment.
The FPGA Desktop Execution Node in the LabVIEW 2013 FPGA Module facilitates the simulation of individual FPGA VIs on the development computer. Based on a configuration dialog, it allows the selection of the appropriate I/O terminals as well as the FPGA clock to be used during the simulation within While Loops, and interaction with models inside of simulation loops using the LabVIEW Control Design and Simulation Module. These simulations have increased timing fidelity with respect to primitives, dynamics of DMA FIFOs, and single-cycle Timed Loops.
Figure 6. The FPGA Desktop Execution Node is a configuration-based simulation harness that provides direct access to I/O terminals and timing resources of the FPGA.
Dynamically Loading Multiple FPGA Interfaces
Dynamically specifying a bitfile at run time gives you the ability to create field upgradeable FPGA-based applications. Traditionally, LabVIEW FPGA users had to use multiple static references using the Open FPGA VI Reference Node to share an FPGA interface with multiple bitfiles.
Figure 7. Before the LabVIEW 2013 FPGA Module, users had to specify static references to manipulate multiple bitfiles.
In the LabVIEW 2013 FPGA Module, you can use the new Open Dynamic Bitfile Reference function to select multiple bitfiles at run time through a given path input. With this function, multiple bitfiles can use a common FPGA interface as long as they share the same named set of controls, indicators, and DMA FIFOs. You can use this function to create more flexible host interfaces for advanced applications.
Figure 8. The LabVIEW 2013 FPGA Module allows the sharing of a single FPGA interface with multiple bitfiles specified at run time by a path input.
Web-Based Bitfile Deployment
New in 2013, you can update the FPGA bitfile on next-generation NI CompactRIO devices through the Web-Based Configuration and Monitoring interface. This process requires only a Silverlight-enabled web browser and an FPGA bitfile, and makes it easier to manage the embedded target’s configuration.
Figure 9. Bitfiles for FPGA chips in CompactRIO targets can now be updated through the Web-Based Configuration and Monitoring interface.
4. New LabVIEW 2012 Features
Proven, NI Recommended Architectures for Control and Monitoring Applications
The new LabVIEW project templates and sample projects for NI Single-Board RIO and CompactRIO hardware provide applications and source code that are designed to scale to a wide variety of control and monitoring applications.
Figure 1. Sample projects provide proven, reliable architecture starting points for embedded control and monitoring applications.
If you’re beginning a new application, the sample projects provide a starting point that can shorten your development time and ensure your design is reliable. If you have an existing LabVIEW RIO application that you would like to optimize or improve, you can use the sample projects to learn LabVIEW FPGA design techniques and architectural best practices that are specific to embedded applications. To learn more about LabVIEW sample projects for control and monitoring applications, watch the LabVIEW Real-Time 2012 Sample Projects Webcast and read the LabVIEW Templates and Sample Projects white paper.
Better Verification of FPGA VI With Execution on Development Computer
Compiling an FPGA VI can take minutes to hours. However, you can test the logic of an FPGA VI before compiling it by running the FPGA VI on a development computer with simulated I/O. When you run the FPGA VI on the development computer, you can use all traditional LabVIEW debugging techniques, such as probes, execution highlighting, breakpoints, and single-stepping. In the LabVIEW 2012 FPGA Module, when you run your FPGA VI on your development PC, you will notice improved fidelity with respect to time when executing multiple single-cycle Timed Loops at the same or different clock rates, and when sharing resources between two or more single-cycle Timed Loops.
Figure 2. Notice improved fidelity when executing your FPGA VI on a development computer.
Floating-Point Support Within LabVIEW FPGA
Previous versions of LabVIEW FPGA required developers to use the fixed-point data type when fractional data was needed. While the fixed-point data type is efficient for hardware-based designs when it comes to speed and resource utilization, it does not provide the flexibility that the floating-point data type offers. In the LabVIEW 2012 FPGA Module, the single-precision floating-point data type is natively supported. Not only does this give users the ability to directly retrieve floating-point data from DMA FIFOs, avoiding an expensive conversion from fixed-point to floating-point on the real-time or Windows host, but it gives DSP designers the ability to solve linear-algebra problems in LabVIEW FPGA that require a wider dynamic range than what fixed-point or integer data type provide. Note that although the floating-point data type offers many benefits, it has limited support when used in single-cycle Timed Loops, and uses significantly more FPGA resources than the fixed-point data type for certain operations.
Figure 3. Floating-point data type is supported in the LabVIEW 2012 FPGA Module.
For more information on the functions and structures that support the floating-point data type, see Functions That Support the Single Precision Floating-Point Data Type in FPGA VIs. For benchmarks that compare floating-point data type resource utilization to fixed-point, see LabVIEW FPGA Floating-Point Data Type Support.
Array and Cluster Support Within Single-Cycle Timed Loops
In the LabVIEW 2012 FPGA Module, Boolean, numeric, and comparison operations within single-cycle Timed Loops now support cluster and array data types. Each primitive operation is parallelized on the FPGA for maximum performance, so you no longer need to break out each operation individually. This idea originated in the LabVIEW FPGA Idea Exchange.
Figure 4. Cluster and array data type support has been added to single-cycle Timed Loops.
Faster Compilations With Support for Linux
When it’s time to compile your LabVIEW FPGA VI, you can iterate faster with new Linux-based FPGA compilation options. Linux-based compilation workers offer substantial performance benefits over Windows-based workers. For large, complex FPGA VIs, NI has seen a significant decrease in compilation times. The performance gains vary based on the specifications of the machine performing the compilation and the size of the FPGA target. Linux-based compilation is available with the LabVIEW FPGA Compile Cloud Service, in addition to remote PC compile works and the LabVIEW FPGA Compile Farm Toolkit. For more information on using Linux machines as a compile worker with the LabVIEW 2012 FPGA Module, see NI LabVIEW FPGA Compilation Options and FPGA Compile Worker Performance Benchmarks.
Figure 5. Linux-Based FPGA Compilation Options
Higher Clock Rates With Single-Cycle Timed Loops
To compile single-cycle Timed Loops at higher clock rates for large streaming applications, the compiler, under certain conditions, can remove enable chain for the single-cycle Timed Loops that have no dataflow dependences. Removing this enable chain decreases routing congestion and improves timing performance. For more information on how to use this new feature, see Improving Timing Performance in Large FPGA VIs.
Array Support With High-Throughput Math Nodes
When designing sophisticated DSP algorithms for high-throughput applications, there is often a need to perform high-throughput math on arrays. In the LabVIEW 2012 FPGA Module, the High-Throughput Math Nodes support fixed-size array inputs, eliminating the need to perform math operations element by element with multiple nodes.
Figure 6. Array Support for High-Throughput Math Functions
Tools for Simplifying IP Reuse
When designing LabVIEW FPGA algorithms, it’s important to be able to reuse the IP that was created for one application within another. Oftentimes, developers find themselves modifying the algorithm they created, so that the FPGA VI compiles in a way that it meets system requirements, such as execution speed, throughput, or latency. When they want to reuse this algorithm for another application with different system requirements, they have to make major modifications to the LabVIEW FPGA source code. LabVIEW FPGA IP Builder is a LabVIEW FPGA add-on that gives you the ability to write one algorithm that you can easily compile for multiple systems for various system requirements, without modifying the source code. For more information, see Get Better Performance and Resource Utilization With LabVIEW FPGA IP Builder.
Figure7. LabVIEW FPGA IP Builder gives you the ability to design an algorithm in LabVIEW, and compile it for multiple applications with different performance requirements.
FIFO Improvements for Faster Streaming
The LabVIEW 2012 FPGA Module includes several new features that improve streaming performance with FIFOs for NI FlexRIO targets for PXI Express. One example is a deeper and wider DMA FIFO. The depth of a DMA FIFO has been increased from 32k samples to 256k samples, which makes it easier to achieve sustainable rates when streaming data at high rates.
Additional improvements to both the DMA FIFO and peer-to-peer FIFO give you the ability to pack small data size elements into a 64-bit array before sending to a host. With this new feature, you can obtain higher transfer rates when transferring smaller data size elements between an FPGA target and host. The number of elements that can be sent with a FIFO depends on the data type of the elements.
Figure 8. Write four 16-bit integers in parallel with DMA and peer-to-peer FIFOs for NI FlexRIO targets for PXI Express.
Improved Ability to Create Reusable SubVIs
You now have the option to use a new LabVIEW FPGA construct, the register, to write lightweight, reusable code for communication between loops executing in parallel. You can think of the register as a single-element memory implemented with flip-flops. Like globals, you can write and read registers in the same or different clock domains. Similar to FPGA I/O, memories, FIFOs, and clocks, registers can be specified via name controls, which is how you write reusable subVIs with registers.
Figure 9. Register functions are consistent with those for memories and FIFOs.
5. New LabVIEW 2011 Features
More Efficient Development
With the LabVIEW 2011 FPGA Module, you can now develop your custom logic and Host VI Interface code quicker and more efficiently. After analyzing the common edit-time operations performed during development, NI improved time-intensive operations, from manipulating host interface functions to opening and closing FPGA VIs.
Figure 1. Module improvements for 2011 reduce the time required for common edit-time operations, which helps you develop your custom logic faster.
Simplified Xilinx CORE Generator IP Access
You can now drag and drop configurable Xilinx CORE Generator IP blocks directly from the LabVIEW FPGA palette onto the block diagram. This streamlines integrating existing communications, math, and even image or video processing IP using the same IP Integration Node introduced in the LabVIEW 2010 FPGA Module.
Figure 2. The new Xilinx CORE Generator IP palette makes it easier to access existing FPGA IP that you can use to speed up your development process.
Expanded Options for Cycle-Accurate Simulation
In addition to executing cycle-accurate LabVIEW FPGA application simulations with the Mentor Graphics ModelSim tool, you can now use the Xilinx iSim environment included with the module. Furthermore, when working with ModelSim simulations, you can now use LabVIEW to quickly create test benches that use cosimulation to validate logic signal propagation, rather than working directly with HDL.
6. New LabVIEW 2010 Features
IP Integration Node
The IP Integration Node replaces the HDL Interface Node as a way to integrate third-party IP. Point the node to existing VHDL or use the built-in compatibility with the Xilinx CORE Generator. This node also automatically creates a simulation model for the IP. Because of this, you can simulate the FPGA diagram on the development computer even if it has CoreGen or straight VHDL. After you have configured the node, you can use the IP just like any other LabVIEW node with inputs and outputs.
New Compilation Features With Compile Farm/Cloud Software and Build Specifications
LabVIEW FPGA now uses build specifications to hold properties of compilations for a particular VI. This helps you organize your compiles and easily experiment with different Xilinx tool configurations. NI also released a toolkit that you can use to create a multimachine compile farm to offload FPGA compiles from their development machines. NI is experimenting with incorporating this technology in the cloud as well. The LabVIEW FPGA Cloud Compile Service, a beta feature for LabVIEW 2010, helps you easily use high-end dedicated machines for lengthy FPGA compilations.
Cycle-Accurate Simulation With ModelSim
LabVIEW 2010 can export the LabVIEW diagram to a set of files that you can analyze in off-the-shelf simulation software. Using these methods, you can run cycle-accurate simulations of your LabVIEW FPGA system. Keep in mind that this feature is for those who have experience with ModelSim and other FPGA design tools.
New and Improved IP
LabVIEW 2010 also features new FPGA IP for statistics, such as mean, variance, and standard deviation; a new complex multiply; a matrix-vector multiply; and a complete implementation for the DSP48E MAC block. New memory IP includes a dual-port read and external DRAM support. Finally, there are CLIP improvements including a Configuration Wizard to replace XML creation and VHDL generic support.
Dynamic Host Interface Wire
Previously, the FPGA interface was difficult to reuse because the FPGA reference wire was strictly typed to the bitfile or VI. As of LabVIEW 2010, NI has created a dynamic reference wire that you can apply to more easily reuse subVIs you build with FPGA interface VIs. Keep in mind that the FPGA VI still features a name-based connection to the registers (front panel controls and indicators). You need to make sure these names are also reusable when using this feature. In addition, you can use the legacy strictly typed wire if needed moving forward.
7. New LabVIEW 2009 Features
Early Size and Speed Resource Estimation
A large portion of user feedback asked for more estimation of the FPGA resource usage before waiting through an entire compile. With LabVIEW 2009, the compiler shows early size and speed estimates of your design after the “synthesis” step and alerts you when this report is ready for viewing.
Timing Violation Debugging With Critical-Path Highlighting
When a timing violation happens, it can be difficult to diagnose the critical path and reduce the timing constraints by programming more efficiently and adding pipeline stages. Now, timing violations give you a window that shows every VI in the critical path and highlights the location of the VI on the FPGA block diagram. The feature even examines subVIs to find the source of a timing violation.
New and Improved High-Throughput Math and Signal-Processing IP
New high-throughput math VIs offer functions, such as sin, cos, and exponential, with the high-speed handshaking protocol that allows the functions to be used in a single-cycle Timed Loop. You not only have new math functions, but you can use them with other functions in a high-throughput signal chain such as Window, FFT, and resample.
Host Integration Features
On the host side, there are two important features in LabVIEW 2009. First, NI has exported a C Interface so that you can talk to your LabVIEW FPGA program running in hardware with C. The functionality includes read and write registers, DMA, and interrupts. Second, LabVIEW 2009 features new scaling companion VIs for certain FPGA IP functions. For example, there is a VI that converts the raw FFT data to a spectrum; a VI that prepares coefficients for FPGA filtering VIs; and a VI that takes frequency, amplitude, and phase and returns values to use with signal generation VIs.
8. New LabVIEW 8.6 Features
Enhanced Behavioral Simulation
For more efficient development, you can use enhanced behavioral simulation to run the code on the development computer and verify functionality before compilation. Additionally, in LabVIEW 8.6, you can use LabVIEW programs that assert test vectors or interactive values to the I/O nodes in the FPGA. Capture the outputs for verification and visualization of FPGA behavior, run the host at the same time as the FPGA on the development computer, and get simulated register and DMA transfers between the simulated FPGA and host code. With these new features, you can create a test bench for the FPGA code and simulate the entire system without always compiling to check logic.
FFT and Other New IP
In LabVIEW 8.6, you can implement fast Fourier transform (FFT) with windowing on the FPGA. This is one of the most requested features, and NI has delivered a customizable IP core that can execute FFT, inverse FFT, multiple bin sizes, and multiple throughput settings. NI also released rational resampling, divide, square root, adaptive filters, and fixed-point overflow handling functions.
The fixed-point data type is now supported on nearly every FPGA function input. This includes support for DMA, memory, filters, PID, FFT, and all arithmetic. Additionally, the fixed-point data type offers an option to add an overflow bit carried on the wire. NI will continue to enhance fixed-point support in the future to work with resource-constrained targets.
Component-Level IP (CLIP)
CLIP is a new way to import and use external IP written in a hardware description language (HDL). Implementations instantiated with CLIP run in parallel with the LabVIEW diagram, and you communicate to them through user-created I/O nodes. With some hardware targets, you can use CLIP to talk directly to I/O pins. CLIP functions open the FPGA platform further to include all types of IP, which may be better suited to run in parallel rather than in data flow like the current HDL Interface Node runs.
9. New LabVIEW 8.5 Features
FPGA Project Wizard
The new FPGA Project Wizard helps you create a complete LabVIEW project with the FPGA target and I/O configured and ready to program. Because it can directly link to the existing FPGA Wizard, you can quickly generate functional code for analog and digital I/O, counter, and quadrature encoder measurements. The FPGA Project Wizard is enhanced with new DMA options for FPGA and host code generation.
Control, Filtering, and Signal-Generation IP
The LabVIEW FPGA Module 8.5 includes new IP in the FPGA palette as well as enhanced existing IP for improved resource use on the FPGA.
- Control: Included in the LabVIEW PID and Fuzzy Logic Toolkit, the PID block in FPGA now works with multiple channels, so you can input an array of channels into the same PID logic on the FPGA. This enhancement is especially important for high-channel-count applications. The number of possible channels rose from eight to 256 for a 1M gate target. Additionally, the single-channel benchmark is three times faster and uses almost 20 percent fewer FPGA resources.
- Filtering: All filters are also compatible with multiple channels. Additionally, LabVIEW FPGA includes a new notch filter, rounding out the existing Butterworth highpass and lowpass filters.
- Signal generation: In addition to the existing sine generator, LabVIEW FPGA now features a square wave generator and noise generators (Gaussian and white).
Modularity and Code Reuse Features
- I/O name controls: Put I/O nodes, methods, and properties inside subVIs to specify the I/O item through a wire.
- Clock controls: Use a wire to specify which clock, such as an onboard or derived clock, to use in a particular single-cycle Timed Loop.
- Enhanced Feedback Node: Place a Feedback Node anywhere in a block diagram to escape the context of a loop. A Feedback Node can be useful for state storage or pipelining and now works anywhere, including subVIs.
LabVIEW Statechart Module
NI now offers additional ways to program FPGAs graphically. Many designers prefer using statecharts to represent the system they want to build. With this new module supporting LabVIEW FPGA, you can not only represent FPGA-based systems with statecharts but also program them with the same visual paradigm.
Pioneer-Level Support for Fixed-Point Data Type
There is a new fixed-point data type in LabVIEW that is especially useful for FPGA programming. Previously, LabVIEW FPGA supported only integers. However, with support for new fixed-point data types, you can bring fractional numbers and arbitrary bit-width data types to FPGA programming. LabVIEW 8.5 features fixed-point support for a small number of primitive math and comparison functions. Future releases may expand support for this important data type.
10. New LabVIEW 8.2 Features
FPGA Math and Analysis IP
The LabVIEW FPGA Module 8.2 provides new native analysis functions so you can reuse code for basic signal processing and control functionalities common to FPGAs. This new IP includes the following:
- Direct current (DC) and root-mean-square (RMS) measurements that calculate the DC, RMS, sum, mean square, and/or square sum values of a signal
- A Butterworth filter, for input signals, that is configurable using the Express VI
- A period measurement that calculates the period of an evenly sampled periodic signal using threshold crossing detection
You can design FPGA I/O and timing for your intelligent data acquisition applications with the FPGA Wizard. Using this configuration-based wizard, you can select the timing and synchronization between your FPGA device and host VI. After selecting your timing, you can configure your analog, digital, counter, or quadrature encoder I/O. When you have configured your I/O, you can save your configuration and generate basic FPGA code and host code. You can then incorporate additional code to complete your application functions such as control algorithms, data logging, or data networking.
New Memory VIs
With the new memory read and write interface, you can access all 80 KB of memory on 1M gate devices and all 190 KB of memory on 3M gate devices. You can use memory to store data for waveform generation or data logging without using arrays that inefficiently use FPGA gates.
11. New LabVIEW 8.0 Features
With a LabVIEW project, you can not only target and open VIs in LabVIEW for Windows and LabVIEW FPGA, LabVIEW Real-Time, and other LabVIEW modules simultaneously but also develop LabVIEW FPGA applications. A LabVIEW project can help you create and manage all FPGA resources, including:
- FPGA I/O
- Custom clocks
- CompactRIO configurations
- FPGA FIFOs
DMA Data Transfers
The LabVIEW FPGA Module 8.0 DMA capabilities eliminate throughput limitations between the FPGA device and host. Although FPGAs on RIO devices can run at rates up to 20 MHz, the fastest data-streaming rate without DMA is approximately 1 MB/s. The module implements DMA on all NI R Series and CompactRIO devices for at least a 20 times increase in data-streaming rates between the FPGA and a host application compared to other implementations such as using interrupt requests.
DMA provides a direct data-to-RAM link on the host machine. Relying on the host processor to stream data from the device to the host often leads to latencies and causes a data transfer bottleneck. Using interrupt requests also consumes processor clock cycles and increases the overall load on a host CPU. With LabVIEW 8.0, you gain more efficient device-to-host and host-to-device data transfers that bypass the CPU, creating a higher performance data acquisition system for all applications.
To use DMA, simply create two memory buffers: one in memory on the FPGA device and another in memory on the host processor. LabVIEW efficiently and transparently transfers data over the PCI bus. The module uses FPGA FIFOs configured for DMA to write and read to DMA memory and uses FPGA invoke methods on the host side to create, write, and read from host memory. DMA significantly enhances RIO hardware for applications such as buffered intelligent data acquisition, communication device digital streaming, in-vehicle data acquisition, and online machine condition monitoring.
Drag-and-Drop FPGA I/O
With LabVIEW FPGA, you can quickly access RIO device I/O through specific device I/O functions. (However, the LabVIEW FPGA function palettes mentioned in this document are specific to FPGA execution targets and contain functions available only when targeted to an FPGA device or FPGA device emulator.) The module gives you direct single-point access to analog and digital I/O on NI RIO hardware. With the LabVIEW FPGA Module 8.0, you can directly drag and drop I/O from the LabVIEW project window onto the block diagram of your FPGA VI.
The module offers many device I/O functions, including:
- Analog input
- Analog output
- Digital input
- Digital output
- Digital port input
- Digital port output
- I/O Method Node
- I/O Property Node
12. New LabVIEW 7.1 Features
Single-Cycle Timed Loop
The LabVIEW Timed-Loop structure executes a loop at the period you specify. Use the Timed Loop to develop VIs with multirate timing capabilities, precise timing, and feedback generation on loop execution or to dynamically change timing characteristics or several execution priority levels. The LabVIEW FPGA single-cycle Timed Loop is a specialized Timed Loop with which you can develop LabVIEW FPGA applications as efficiently (in terms of speed and space) as hand-coded HDL programming. The single-cycle Timed Loop is similar to a clocked process in VHDL. All of the LabVIEW code in the loop is combinatorial logic on the FPGA, where inputs are from components such as digital input functions, controls, or left-shift registers and outputs are digital output functions, indicators, and right-shift registers. It is easy to take advantage of a single-cycle Timed Loop—use it as you do a standard While Loop.
The single-cycle Timed Loop ensures that all code within the loop executes in a single clock cycle (25 ns). Although there are some limitations to the single-cycle Timed Loop, such as ensuring that all the code inside it can execute within a clock cycle, using it can result in extremely efficient code for executing digital I/O and simple logic and signal processing.
HDL Interface Node
You can integrate existing HDL IP directly into a LabVIEW FPGA VI using the HDL Interface Node and represent this code as a single function block within LabVIEW. You then can reuse this code within the same application or in other applications using the same function block. If you have a block of HDL code to use in an FPGA VI, you can either enter your VHDL code directly into the HDL Interface Node or refer to external .vhd files rather than rewriting the code in LabVIEW.
13. Next Steps
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