NI VeriStand Engine Architecture

Publish Date: Jul 16, 2013 | 2 Ratings | 4.50 out of 5 | Print


The NI VeriStand Engine is the execution mechanism that is responsible for executing hardware I/O, models, procedures, alarms, and other test system tasks that are specified in the system definition file. The engine controls the timing of the entire system as well as the communication between the NI VeriStand Engine and the workspace. This article describes the NI VeriStand Engine architecture and provides insight into how NI VeriStand handles important real-time components such as priority, communication, hardware I/O, and model interfacing.

Table of Contents

Understanding the NI VeriStand Engine

The NI VeriStand Engine consists of multiple Timed Loops whose execution timing is controlled by hardware events with microsecond resolution. Deterministic memory buffers called FIFOs provide communication between tasks in different loops without inducing jitter into engine execution. With this multiloop architecture, the NI VeriStand Engine naturally takes advantage of the parallel processing power of multicore processors, increasing system performance. You can configure a variety of engine execution settings when creating the system definition. For example, you can choose between high-throughput, parallel and low-latency, and sequential architectures. Additionally, the NI VeriStand Engine publishes a variety of system health parameters that you can access at run time. For more in-depth system analysis, you can use the NI Real-Time Execution Trace Toolkit, which offers greater visibility into your application’s execution.


Figure 1. Loops and Communication Paths in the NI VeriStand Engine

The engine’s real-time I/O tasks use a hardware-timed, single-point I/O structure that is ideal for simulation, control, and point-by-point analysis tasks. However, you can also add support for higher-speed, buffered signal generation and acquisition using an NI VeriStand custom device discussed in the article Building Custom Devices for NI VeriStand.

The NI VeriStand Engine can run on PCI- and PXI-based real-time systems from National Instruments as well as NI CompactRIO and NI Single-Board RIO interfaces that have 128 MB of DRAM or greater. A real-time system gives you the ability to execute your tests deterministically with synchronized I/O – a critical capability for applications that are implementing closed-loop control or system simulations that interact with real-world components. However, for systems with lower performance needs or for implementing model-in-the-loop (MIL) or software-in-the-loop (SIL) tests, you can also run the NI VeriStand Engine on the same computer as your user interface.


NI VeriStand Engine Loop


Default Execution Rate

Primary Control Loop H 100 Hz
Model Execution Loop(s) M Decimation of the Primary Control Loop rate
Asynchronous Custom Device Loop(s) H/M/L User defined
Waveform Processing Loop L Event Driven
DAQmx Waveform Producer Loops L 10 Hz; can be defined by user
Data Processing Loop M Decimation of the Primary Control Loop rate
Communication Send Loop L 15 Hz
Communication Receive Loop L Event driven
XNET Loop L 100 Hz
DIO Loop L Decimation of the PCL rate
Model Interface Loop L Event driven

Table 1. Priority and Default Execution Rate for the Loops of the NI VeriStand Engine


Individual Loops in the NI VeriStand Engine

Primary Control Loop
The Primary Control Loop controls the timing for the NI VeriStand Engine and maintains the most up-to-date table of channel values. Per iteration, the Primary Control Loop executes the following tasks:

  • Reads and writes high-speed FPGA I/O, analog and counter DAQ I/O, and Asynchronous Custom Device Loop data
  • Applies scaling to the data
  • Executes one step of the stimulus profile, if a test is currently running
  • Sends data to the Data Processing Loop to synchronize the table of channel values
  • Sends data to the Model Execution Loops
  • Prompts the Data Processing Loop, Model Execution Loop(s), and Custom Device Loop(s) to execute
  • Performs software fault insertion
  • Creates mapping connections
  • Executes inline custom devices
  • Reads status information from the Waveform Processing Loop and DAQmx Waveform Producer Loop(s)

Model Execution Loop(s)
Each Model Execution Loop executes a corresponding compiled model. The number of Model Execution Loops is determined by the number of models specified in the system definition file. Per iteration, each Model Execution Loop executes the following tasks:

  • Reads the data sent by the Primary Control Loop and maps this data to model inputs
  • Executes one step of the model
  • Reads model output values and sends this data to the Primary Control Loop

Asynchronous Custom Device Loop(s)
Each of the asynchronous custom devices runs in its own loop. When you create a custom device, you determine the number,behavior, and priority of Custom Device Loops. The NI VeriStand Engine is responsible only for initiating the Custom Device Loop execution and for transmitting the custom device input data values per iteration of the Primary Control Loop. The loop inside the custom device is responsible for the execution rate of the custom device.

Waveform Processing Loop
The Waveform Processing Loop performs the following actions to transfer waveform data through the system:

  • Reads waveform data from DAQmx Waveform Producer Loops.
  • Sends waveform data to the VeriStand Gateway.
  • Reads waveform data from custom devices.
  • Sends waveform data to custom devices.

DAQmx Waveform Producer Loop(s)
DAQmx Waveform Producer Loops acquire waveforms from DAQ devices. Each waveform task in the system definition has a corresponding DAQmx Waveform Producer Loop that performs the following actions:

  • Reads waveform data from analog input channels on DAQ devices using the timing and triggering settings you define in the task.
  • Sends waveform data to the Waveform Processing Loop.
  • Logs acquired data to .tdms files, if you enable logging.

Data Processing Loop
Like the Primary Control Loop, the Data Processing Loop maintains a complete copy of the channel values table. The Data Processing Loop executes procedures, alarms, and calculated channels, as well as distributes among the loops of the engine the execution commands received by the Communication Receive Loop. Per iteration, the Data Processing Loop executes the following tasks:

  • Receives the table of channel values from the Primary Control Loop
  • Executes procedures, alarms, and calculated channels
  • Transmits updated table of channel values to the Primary Control Loop
  • Sends data values to the Communication Send Loop

Communication Loops
The Communication Loops maintain TCP/IP communication with the NI VeriStand Gateway. There are two Communication Loops:

  • Communication Send Loop - transmits channel values to the NI VeriStand Gateway
  • Communication Receive Loop - listens for execution commands sent by the NI VeriStand Gateway

NET Loop
The XNET Loop is responsible for reading and writing NI-XNET data. This could contain CAN, LIN, or FlexRay data depending on the type of communication that is configured in the system definition. 

DIO Loop
The DIO Loop reads and writes low-speed digital input and output data from National Instruments data acquisition modules.  

Model Interface Loop
Simulation model inputs are typically broken into inports and parameters. Inports are designed to take in dynamic data, and parameters are often static. Model Execution Loops handle the high-speed dynamic data that interacts with model inports and outports, while the Model Interface Loops take in low-speed asynchronous updates from model parameters.


Additional Resources

Watch the NI VeriStand Demonstration Videos

Compare the NI VeriStand Development Environments

Browse the NI VeriStand Add-Ons


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