Use DDCs for High-Speed RF/IF Streaming

Publish Date: Mar 05, 2007 | 3 Ratings | 5.00 out of 5 | Print | Submit your review

An integral part of many RF/IF communications systems is a digital downconverter (DDC).

To understand the function of the DDC, first look at a typical RF system. This system may involve multiple analog upconversion and downconversion stages that convert the signal from radio frequency (RF) to intermediate frequency (IF) and vice versa. On the acquisition side, the downconverted IF signal is digitized and then demodulated and processed in software.

To understand an area for performance improvement in this scheme, consider the example of recording a 1 MHz signal centered at 40 MHz. This signal could be the result of the analog RF-to-IF downconversion, or it could be the original signal itself. The 40 MHz IF signal is digitized by a 14-bit, 100 MS/s digitizer, resulting in 200 MB/s of data. This far exceeds the bandwidth limitation of PC buses such as PCI, USB, or LAN. Hence, the signal recording length is limited by the digitizer’s onboard memory, which permits recording for a few seconds at most.

The DDC frequency shifts the 1 MHz IF signal centered around 40 MHz down to baseband, thereby reducing the digitizer sample rate requirement from 100 MS/s to 2 MS/s, a 50X improvement in speed.


To digitally record an RF signal for an extended period of time, digital downconversion offers a solution. In this case, the signal of interest is a 1 MHz narrowband signal, which represents only a small portion of the spectrum. Remember, you need to record only the 1 MHz signal centered around 40 MHz, not the entire Nyquist bandwidth of the analog-to-digital converter (ADC). By multiplying the incoming signal with a numerically controlled oscillator (NCO), which generates a digital sinusoid with a frequency equal to that of the incoming signal (40 MHz in this example) in the FPGA, the DDC effectively shifts the 1 MHz signal of interest to baseband. As with analog down-conversion, digital downconversion introduces images, which are then filtered out digitally in the FPGA. Thus far, the downconversion process has moved the signal from IF to baseband, but to realize the benefit of this technique, the digitized waveform, originally sampled at 100 MS/s, needs to be reduced in size. The next step is decimation, in which the digitized waveform is decimated in the FPGA to reduce the effective sample rate to approximately 2 MS/s. This represents a 50X time improvement in performance and amounts to only 4 MB/s, which you can stream indefinitely over most PC buses.

By focusing on the region of interest, the DDC greatly reduces the data rate so you can stream RF/IF signals continuously. In addition to providing a DDC, some digitizers such as the NI 5142 onboard signal processing (OSP) digitizers leverage the DDC architecture to provide alias-protected decimation for baseband I/Q signals by bypassing the downconversion stage.

Learn about a 100 MS/s, 14-bit digitizer with 40 MHz DDC.

Learn more about new RF/IF products for streaming applications.

This article first appeared in the Q3 2006 issue of Instrumentation Newsletter.

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