Quadrature Encoder Example DAQ Personality

Publish Date: Aug 24, 2016 | 2 Ratings | 4.50 out of 5 | Print | 1 Customer Review | Submit your review


This white paper is part of the Introduction to Programming With NI R Series. It specifically describes the quadrature encoder example personality, which was designed to target high-channel-count needs for both quadrature encoder output and input. This personality has eight quadrature encoder channels configurable for input or output. The attached host example configures it for six quadrature encoder inputs and two quadrature encoder outputs.

Download the Quadrature Encoder Example DAQ Personality.

Table of Contents

  1. LabVIEW FPGA Personality
  2. LabVIEW Host Personality
  3. Conclusion
  4. Additional Resources

1. LabVIEW FPGA Personality

The NI LabVIEW FPGA code is the portion of this code embedded on the R Series board. The code defines the FPGA in the same way an ASIC defines a multifunction data acquisition (DAQ) board. It was written with LabVIEW FPGA and compiled into a bitfile. It is in its finalized form and does not require you to use the LabVIEW FPGA Module. However, you do need LabVIEW FPGA to customize this code. 

This LabVIEW FPGA personality implements the single-cycle Timed Loop architecture, with each loop dedicated to specific DIO lines. See the block diagram for the LabVIEW FPGA code in Figure 1.

Figure 1. Block Diagram of the LabVIEW FPGA Code


Quadrature Encoder

Each single-cycle Timed Loop on the block diagram is dedicated to a particular set of DIO lines and has the flexibility to perform quadrature encoder output or input. This functionality is defined by a simple Case structure and Boolean control. If the Boolean is set to a false value, the DIO lines will be used for quadrature encoder output. If the Boolean is set to a true value, the DIO lines will be used for quadrature encoder input. Figure 2 shows these two cases.

Figure 2. Single-Cycle Timed Loop Dedicated to DIO Lines 0 Thru 2 (Both Cases)


Quadrature Encoder Input

For quadrature encoder input, three digital lines are monitored at the rate of the FPGA clock (40 MHz in this case). These three digital lines are the A, B, and Z quadrature encoder inputs. Figure 3 shows these digital lines and the algorithm for determining position. 


Figure 3. Quadrature Encoder Input Logic (Contained in a subVI)


Quadrature Encoder Output

For quadrature encoder output, the FPGA code is also run at the rate of the FPGA clock. The user specifies the direction and rate for the quadrature encoder output. See the quadrature encoder output algorithm in Figure 4. 

Figure 4. PWM Output Logic (Contained in a subVI) 


Digital I/O

The LabVIEW FPGA architecture makes it simple to add additional loops in parallel without affecting other parts of the FPGA application. For this reason, the LabVIEW FPGA code also takes advantage of the remaining DIO lines by configuring all of Connector 1 as static digital outputs and all of Connector 2 as static digital inputs. See this FPGA code in Figure 5.

Figure 5. Static DIO Logic


Back to Top

2. LabVIEW Host Personality

The LabVIEW host code acts as the user interface used to communicate with the FPGA. The host code interacts directly with the FPGA code by updating controls and reading from indicators on the front panel of the FPGA code. This functionality is supported by the NI-RIO driver. 

This example personality consists of three main portions:

1.      Open a reference to the FPGA bitfile on the target R Series board.

2.      Use a Read/Write Node to update controls and indicators on the FPGA front panel.

3.      Close the reference to the FPGA bitfile.


Block Diagram

See the example host block diagram in Figure 6.

Figure 6. Block Diagram of the LabVIEW Host Code


These three main steps describe the overall setup of the host VI. This host code is a little more complex because of conversions that must take place prior to writing to a control. The following sections explain these three main steps in more detail:

1.      Open Reference to Target FPGA

Figure 7. First Part of the Host Code


The first part of the code is the initialization stage. In this part, the resource name for the target R Series board is passed to the Open FPGA VI Reference. This function opens a reference to the board that can be used by any subsequent functions or subVIs that communicate with the FPGA. The reference is then passed to the Read/ Write Node and the digital lines are initialized to function as an output or input. 

2.      Read FPGA Indicators and Write to FPGA Controls

Figure 8. Middle Part of the Host Code


The middle part of the code consumes the majority of the execution time for this host VI. This part of the code consists of a While Loop with a Read/Write Node inside of it. The Read/Write Node gives users the ability to write to controls and read from indicators on the front panel of the FPGA code. In Figure 8, each input to the node is a control in the FPGA code. 

For example, Reset - Quad 0 is the name of a control in the FPGA code. This particular control resets the quadrature encoder position count stored on the FPGA. The corresponding indicator Encoder Position - Quad 0 returns the current quadrature encoder position that is stored on the FPGA.

While LabVIEW FPGA supports fixed-point and floating-point data types, integer data types are the most efficient to use when it comes to consuming FPGA resources. For this reason, any data returned from the FPGA to the host code will be a U32. The intermediate subVI called Ticks to Deg converts the U32 to a double data type in degrees.   

The While Loop executes at a rate defined by the Wait Until Next ms Multiple function. In this case, the user has defined the wait as 100 ms. This means that the While Loop executes every 100 ms, or at a rate of 10 Hz. 

3.      Close the FPGA Reference


Figure 9. Final Part of the Host Code


The final part of the host VI closes the reference to the R Series board. It also handles any errors that occurred during the execution of the host VI. 


Front Panel

The host code front panel layout is in a quadrant form. Quadrature encoder is on the left, DIO is on the right, inputs are on the top, and outputs are on the bottom. Figure 10 shows the front panel.

Figure 10. Front Panel of the LabVIEW Host Code


Back to Top

3. Conclusion

You can use this example personality for high-channel-count quadrature encoder. You do not need the LabVIEW FPGA Module to use this personality. However, you do need the module if you want to make any modifications to the FPGA code. The NI-RIO driver is the only driver you need to use this example personality.


Quadrature Encoder Example DAQ Personality


Back to Top

4. Additional Resources



Back to Top

Customer Reviews
1 Review | Submit your review

  - Oct 5, 2007

Figure 3 exhibits appears to suffer from a race condition flaw. The 'Source A' value could be written to the 'A Register' indicator <b>before</b> 'A Register' local variable is read. If this happens, a quad state change can be missed. Ditto for 'B Register'. Caveat: I don't use FPGA module, comment based on typical LabVIEW sequencing and parallelism rules. -Kevin P.

Bookmark & Share


Rate this document

Answered Your Question?
Yes No