64-bit Counter Example DAQ Personality

Publish Date: Aug 24, 2016 | 1 Ratings | 4.00 out of 5 | Print | Submit your review


This white paper is part of the Introduction to Programming With NI R Series. This example personality for R Series devices features 16 simple-event counters with 64-bit resolution each. With the ability to count up to 264–1, these counters can essentially count forever (over 14,000 years at 40 MHz). In addition to being the highest in resolution and channel count, this personality gives you the ability to specify the terminal count, generates output pulses when the terminal count is reached, and provides filtering capability to remove noise and glitches from the source signal.

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Table of Contents

  2. LabVIEW Host VI
  3. Sixteen 64-bit Counter Pinouts
  4. Conclusion
  5. Additional Resources


Each 64-bit counter is implemented using a single-cycle Timed Loop, which guarantees that all operation executes in one clock pulse at 40 MHz internal timebase. The single-cycle Timed Loop runs continuously with start and stop states. The start state enables the counter task while the stop state disables the counter operation and reinitializes the counter. Two subVIs (Edge Counter and Pulse Generator) are called in the start state as shown in Figure 1.

Figure 1. One 64-Bit Counter Loop in LabVIEW FPGA

Edge Counter


This subVI performs digital edge counting by outputting the current counter register value and the state of terminal count based on the signal inputs (Source and Gate defined by the FPGA I/O Nodes) and the configured counter parameters. Counter Parameters defines the configurable counter task options, which include the following:

    • Edge—Specifies either to count on the rising or falling edge of the digital signal
    • Count Direction—Specifies whether to increment or decrement the count register
    • Terminal Count—Specifies the terminal count value up to 264–1
    • Output Pulse—Specifies how long in microseconds the terminal count output pulse will stay high
    • Ticks to Filter—Specifies the number of ticks that must occur to determine a rising/falling edge of a signal
    • Gate—Specifies whether to gate the source signal


Pulse Generator


This subVI generates a pulse signal passed to the counter output line whenever a terminal count is reached. The duration of the high state of the pulse is specified by the Output Pulse value. The counter register can also be reset to the default initial value based on the count direction. In essence, the counter register resets to 0 when counting up, and Terminal Count value when counting down.


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2. LabVIEW Host VI

Figures 2 and 3 show a typical host VI that performs digital event counting task on a counter using the FPGA personality described earlier. This task simply counts the number of rising or falling edge on the source signal and either increments or decrements the counter register. The front panel in Figure 2 specifies the resource name, counter parameters, and the counter register.


Figure 2. Digital Edge Count Host VI Front Panel

The corresponding host VI block diagram in Figure 3 is similar to NI-DAQmx counter task programming for the multifunction DAQ and counter board. Figure 4 shows a typical counter task configuration using NI-DAQmx.


Figure 3. Digital Edge Count Host VI Block Diagram


Figure 4. NI-DAQmx Digital Event Counting 


As indicated in Figure 4, the counter task can be divided into the following five stages:

  1. Configures the R series device by specifying the resource name and the 64-bit counter personality using the Open FPGA Reference
  2. Configures the counter parameters using the FPGA Read/Write Node, which can be expanded to accommodate additional counter tasks
  3. Starts the counter task
  4. Reads the current counter register value and the state of terminal counter output pulse; the counter can also be reset to reinitialize the counter register to the default state based on the count direction
  5. Clears the counter task and close reference to the FPGA personality

This sample host VI can also be modified to include up to 16 additional counter tasks. Figures 5 and 6 show the front panel and block diagram of digital edge count event tasks for four counters. In Figure 6, each FPGA Read/Write Node was simply expanded and configured for each additional counter.


Figure 5. Digital Edge Count (Four Counters) Front Panel


Figure 6. Digital Edge Count (Four Counters) Block Diagram


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3. Sixteen 64-bit Counter Pinouts

Figure 7 below shows the counter pinouts defined on the FPGA. The product manual for the R Series boards provides further information on the physical device pinouts for the digital lines.

Figure 7. Counter Device Pinouts on FPGA

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4. Conclusion

This example personality was designed for counting up to 264–1 digital events. You do not need the LabVIEW FPGA Module to use this personality. However, you do need the module to make any modifications to the FPGA code. The NI-RIO driver is the only driver necessary.


64-bit Counter Example DAQ Personality


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5. Additional Resources

Browse NI R Series Products

Advanced Data Acquisition Techniques With NI R Series

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