High-Throughput Data Streaming with the NI PXIe-5644R

Publish Date: Nov 21, 2013 | 0 Ratings | 0.00 out of 5 | Print | Submit your review

Overview

The VST High Throughput Streaming (NI PXIe-5644R) sample project demonstrates the following tasks:
  • Streaming data from RF IN of the NI PXIe-5644R (NI 5644R) device to a log on the host
  • Streaming data from the host VI to RF OUT of the NI 5644R

Table of Contents

  1. Features
  2. Sample Project Overview
  3. Running this Example Project

1. Features

The NI PXIe-5644R:

  • Is designed for re-routing data streams to and from the host, other FPGAs, or on-FPGA loopback
  • Reduces data sent to host by applying frequency shifting and decimation on the FPGA
  • Includes an input stream controller that supports burst mode for intermittent streams
  • Provides synchronization for deterministic response times and MIMO systems
  • Supports high-throughput streaming for speeds up to 960 MS/s

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2. Sample Project Overview

This sample project contains two host VIs, which run on the host computer, and an FPGA VI that runs on the FPGA in the NI 5644R. Each host VI configures the RF input and RF output hardware and sets up a data stream between the host VI and the NI 5644R. 

The two VIs are called High Throughput Streaming - From Disk and High Throughput Streaming - To Disk. Descriptions of these VIs follow.

High Throughput Streaming - From Disk

  1. The host VI writes data to the host-to-target direct memory access (DMA) first in, first out memory buffer (FIFO). You can see this FIFO in the Project Explorer window at My Computer»PXIe-5644R»FIFOs»Output Stream»Output Stream FIFO.
  2. The FPGA VI reads from this DMA FIFO, processes the data, and sends it to RF OUT.

High Throughput Streaming - To Disk

  1. The FPGA VI acquires I/Q data from RF IN, processes the data, and writes it to the target-to-host DMA FIFO. You can see this FIFO in the Project Explorer window at My Computer»PXIe-5644R»FIFOs»Input Stream»Input Stream FIFO.
  2. The host VI reads from this DMA FIFO and displays the I/Q data on the front panel.

In both VIs, streaming is accomplished by using DMA channels. One DMA channel is used to stream data from the host to the FPGA. Another is used to stream data from the FPGA to the host. Each DMA channel consists of two FIFOs—one on the host and one on the FPGA.

The output stream uses a start trigger to begin generating data to RF OUT. After the stream starts, the host streams data to the FPGA until you stop the application. If the host does not write data to the FPGA quickly enough, the DMA FIFO does not have enough data to be read, so the FPGA reports a buffer underflow.

You can view the host VIs in the Project Explorer window by expanding My Computer:

  • High Throughput Streaming - From Disk.vi—Streams I/Q data from a TDMS file to RF OUT.
  • High Throughput Streaming - To Disk.vi—Streams I/Q data from RF IN to a TDMS file.

Modified Streaming Design VIs

  • High Throughput RF Output Stream Write Stream.vi—Used in the High Throughput Streaming - From Disk.vi to write the IQ data to the steam. This VI has been modified to acquire a write region from the FPGA, which is handed off to technical data management streaming (TDMS) to read from disk. TDMS releases the region when it finishes reading from disk.
  • High Throughput RF Input Stream Read Stream—Used in the High Throughput Streaming - To Disk.vi to read the IQ data from the steam. This VI has been modified to acquire a read region from the FPGA, which is handed off to TDMS to write to disk. TDMS releases the region when it finishes writing to disk.

FPGA VI

High Throughput VST Streaming (NI PXIe-5644) (FPGA).vi—This is the FPGA VI used for both the High Throughput Streaming - From Disk.vi and High Throughput Streaming - To Disk.vi host VIs. This VI reads data from the host-to-target FIFO and writes data to the target-to-host FIFO in parallel. This allows generation and acquisition at the same time. Additional controls are included to let the host control features on the FPGA such as the throughput rate (up to 960 MS/s), the number of elements to read, and the number of elements to write. Indicators are included to notify the host about the FIFO status, if the FIFOs timed out, the minimum number of elements to write, and the max throughput.

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3. Running this Example Project

  1. Ensure all hardware is set up and visible in NI Measurement & Automation Explorer (MAX). Note the resource names of all NI 5644R devices; you will need these names later.
  2. Connect the appropriate equipment to RF IN and RF OUT on the NI 5644R.
  3. In the Project Explorer window, open My Computer»High Throughput Streaming - From Disk or High Throughput Streaming - To Disk
  4. In the RIO Device pull-down menu, specify the resource name of the NI 5644R that you identified in Step 1.
  5. Click Run. The front panel displays acquisition progress, the status of the buffer, and the FIFO fullness.
  6. Wait for the acquisition or generation to finish or click Stop to end the program.
  7. Experiment with different values of the front panel controls and click Run. You must restart the VI for new settings to take effect. You also can open and run the other host VI.

 

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Attachments:

vst_streaming_v1.0.zip

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