LabVIEW FPGA Manchester Encoding and Biphase SPDIF Decoding Reference Examples

[ExamplePrograms]

Overview

The examples provide a reference for encoding and decoding biphase modulated digital data streams in LabVIEW FPGA. One of the biphase encoding schemes shown in the commonly used Manchester encoding. A second project includes examples for acquiring nd decoding a S/PDIF digital audio data stream.

The ZIP files contains two LabVIEW projects with a number of LabVIEW FPGA examples showing the implementation of bi-phase encoders and decoders. Unzip the contents of the file to an empty directory.

Biphase Generation

Simple Bi-phase Generator

Example of basic digital communication bi-phase encoding. This example streams a sequence of bytes to a digital output line using the selected bi-phase encoding scheme. The bit rate for the output can be selected. This example only generates the raw data and does not prepend and header or synchronization bits which would be necessary for a receiver to accurately acquire and process the data.

Generate Manchester Signal

Basic example showing generation of a Manchester encoded data stream. The data to be sent is generated in one loop and passed to a FPGA FIFO. The subVI which generates the Manchester data stream reads the data bytes form the FIFO and passes them to the digital output. The subVI prepends a simple header to each data packet which allows a reader (see next example) to synchronize and acquire/parse the data. The header consists of a thee half bit pulse followed by a one half bit pulse. The three half bit pulse is not a valid component of regular Manchester encoding and can therefore be differentiated from the rest of the protocol. In addition it can be used by the receiver to to easily measure the bit rate of the protocol. By dividing the length of the three half bit pulse in half (3/4 of a bit), the receiver has a measure to differentiate between full and half bit pulses in the rest of the protocol.

Generate and Read Manchester Signal

An extension of the previous example which adds a Manchester receiver subVI. You must physically wire the digital output channel to your input channel to loop back the data outside the I/O connector of your FPGA R series card or C series module. The Manchester receiver subVI is expecting the data packet to be prepended by a header as explained in the previous section.

S/PDIF Input

This project includes two very similar FPGA VIs which illustrate acquiring and decoding a S/PDIF data stream using a LabVIEW FPGA Single Cycle Loop (SCL). The only difference between these two VIs is the update of the analog output channels using the decoded and extracted audio samples. This allows you to monitor the audio which is acquired by the example using a pair of headphones or speakers connected to the analog output channels of an R series device.

The timing constants placed in the FPGA code are specific to a SPDIF data stream with an audio scan rate of 48 kHz. These values and VIs will not work for SPDIF streams using a different scan rate. To customize the VIs you must adjust the timing threshold values accordingly.

The host VIs provided in the project illustrate extracting and monitoring the audio and raw S/PDIF data.

Additional host and FPGA diagnostic VIs are provided to read the digital signal and verify proper cabling and acquisition.

Hardware Configuration

This project is configured for a PXI RT target and a PXI-7831R FPGA card. The I/O channels are configured to be DIO0 on Connector 0 for the SPDIF Input signal and Analog Out 0 and 1 on Connector 0 for the audio output.

The S/PDIF signal connected to the digital input needs to be compatible with the TTL input levels of the digital lines of the R series device. For testing, the digital audio output of a Creative® Sound Blaster® Live!™ 5.1 card was used.

The configuration in the project can be changed to use other R series devices or to move the R series device to a Windows target. LabVIEW Real-Time is not required for this example to be operate properly.