Triggering Use Cases with 653x Devices

Publish Date: Nov 21, 2013 | 0 Ratings | 0.00 out of 5 | Print | Submit your review

Overview

The following document details some of the triggering use cases with the 653x devices and solutions for solving them. It also provides the names and locations of LabVIEW VIs that can be used to accomplish the tasks.

Use case #1:
I would like to start acquiring (or generating) data when I receive a trigger, acquire (or generate) N samples after the trigger, and stop.

Solution #1:
Configure a finite pattern input (or output) operation with a start trigger.

  • Input: Read Dig Chan-Int Clk-Dig Ref.VI

    To configure the VI, select the physical channel and PFI input for the digital trigger. The example sets up the finite acquisition, configures the trigger, and then waits for the trigger before starting the task.

    This VI can be found in the NI Example Finder:
    Hardware Input/Output»DAQmx»Digital Measurement»Voltage»Read Dig Chan-Int Clk-Dig Ref.VI
  • Output: Write Dig Chan-Int Clk-Dig Start.VI

    To configure the VI, select the physical output channel and PFI input for the digital trigger. This examples loads a waveform into the hardware buffer and on receipt of trigger the generation is initiated.

    This VI can be found in the NI Example Finder:
    Hardware Input/Output»DAQmx»Digital Generation»Voltage»Write Dig Chan-Int Clk-Dig Start.VI

Use case #2:
I would like to start acquiring (or generating) data when I receive a trigger and continue acquiring (or generating) until I stop the operation in software (i.e., press the Stop button) or until an error occurs.

Solution #2:
Configure a continuous pattern input (or output) operation with a start trigger.

  • Input: contreaddig-extclk-digstart.vi

    To configure the VI, select the physical channels and external digital start line.

    This VI is attached for download at the beginning of this document.
  • Output: Cont. Gen. Voltage Wfm.- Int Clk-DigStart.VI

    This VI can be found in the NI Example Finder:
    Hardware Input/Output»DAQmx»Analog Generation»Voltage»Cont. Gen Mult Volt Updates- Int Clk-Dig Start.VI

Use case #3:
I would like to start acquiring data when the input pattern matches (or does not match) a specified pattern.

Solution #3:
Configure a pattern input operation with a start trigger and pattern matching. The 653x devices can be configured for a finite pattern input operation that acquires N samples after the input pattern is matched (or not matched). Alternatively, the 653x devices can be configured for a continuous pattern input operation that continues until an error occurs or until the user stops the program after a pattern match (or mismatch)

  • Finite Acquisition  Read Dig Chan-Int Clk-Pattern Match Start.vi

    This VI acquires N samples when the input pattern is matched.

    This example can be found in the NI Example Finder:
    Hardware Input/Output»DAQmx»Digital Measurements»Read Dig Chan-Int Clk-Pattern Match Start.VI
  • Continuous Input: contdig-intclk-pmatchstart.vi

    This VI acquires continuously while the input pattern is matched. The acquisition is halted when the user clicks the Stop button.

    This VI is attached for download at the beginning of this document.

Use case #4:
I would like to acquire N samples before a trigger and M samples after it.

Solution #4:
Configure a finite input operation with a reference trigger.

  • Read Dig. Chan-Int Clk-Dig Ref.VI

    A reference trigger will allow you to continuously acquire and discard samples until a trigger is received. On this trigger you will then retain a finite number of pre-trigger samples and a finite number of post-trigger samples. You will specify the total number of samples, the digital trigger source (PFI or RTSI line) and number of pre-trigger samples.

    This example can be found in the NI Example Finder:
    Hardware Input/Output»DAQmx»Digital Measurements»Read Dig. Chan-Int Clk-Dig Ref.VI

Use case #5:
I would like my input sample to match (or not match) a specified pattern. When that happens, I would like to acquire N samples before that matched (or mismatched) pattern and M samples after it.

Solution #5:
Configure a finite pattern input operation with a stop trigger and pattern matching.

  • readdigchan-intclk-patmatch.vi

    This example uses a Pattern Match reference trigger to start a finite acquisition. You must configure the Total Number of Samples, Pattern to Match, and Pre-trigger Samples. The Pattern to Match is 8 bits (or however many bits wide you are sampling). The post-trigger samples will be: Post-trigger samples = Total Number of Samples - Pre-trigger samples

    This VI is attached for download at the beginning of this document.


Use case #6:
I would like to acquire data when I receive a start trigger and stop acquiring data when I receive a stop trigger. I do not know how many samples there are between the triggers.

Solution #6:
Unfortunately, DAQmx does not have a explicit Stop Trigger. However, the following options may provide workarounds.

  • Option 1:
    Start a continuous acquisition with one of the trigger examples listed above, use a front panel boolean input to stop the acquisition manually.
  • Option 2:
    Use a Pause trigger to pause the digital acquisition task.
  • Option 3:
    Possibly implement a Change Detection event, fire a event structure and then stop the acquisition.

Use Case #7
I would like to level trigger my 653x device: acquire (or generate) data at specified frequency when my trigger level is high.

Solution #7:
The 653x device does not support level triggering.

  • Option 1:
    Configure the 653x device for a pattern input (or output) operation with an external clock, and configure a counter to generate a clock when the trigger level is high. The disadvantages of this option are:
    1. It requires two devices, and
    2. The frequencies a counter can output are integer divide-downs from a timebase. If you need a specific frequency that can not be achieved by the counter, then this option will not work

Counter Output: Gen Dig Pulse Train-Finite-Retriggerable.V
Input: Cont Read Dig Chan-Ext Clk.VI

The Counter Output is retriggerable when a Digital Trigger is received. This example allows you to configure the number of pulses output at a specific rate when a Digital Trigger is received on a specified PFI input. The Digital Input will allow you specify a External Clock source, this combined with a extended Timeout will allow you to effectively Re-trigger the Digital Input task. These VI's can be found in the NI Example Finder:

The Counter Output example can be found in the NI Example Finder:
Hardware Input/Output»DAQmx»Generating Digital Pulses»Generate Digital Pulse Train-Finite-Retriggerable.VI

The Digital Input example can be found in the NI Example Finder:
Hardware Input/Output»DAQmx»Digital Measurement»Cont Read Dig Chan-Ext Clk.VI

  • Option 2:
    Configure the 653x device for a pattern input (or output) operation with an external clock. Use an external function generator to generate the specific frequency and build external AND circuitry to AND the level trigger with the external clock signal. Feed the output of the AND gate to the clock input of the 653x device.

    Input: Cont. Read Dig Chan-Ext Clk.vi
    Output: Cont Write Dig Port-Ext Clk-Non Regeneration.vi

    For both VIs, you will need to set the clock source to "external" and connect the REQ pin to the output of a counter which generates the clock signal.

    These examples can be found in the NI Example Finder:
    Hardware Input/Output»DAQmx»Digital Measurements (or Digital Generation)»Cont. Read Dig Chan-Ext Clk.VI (or Cont Write Dig Port-Ext Clk-Non Regeneration.VI)


Use Case #8
I would like to use any of the above trigger use cases and also configure the 653x device to re-trigger.

Solution #8:
Re-triggering is not supported by the 653x hardware.

  • Option 1: Perform a finite acquisition and then restart the task.

    readdig-intclk-ref-swretrg.vi

    This example configures a digital input task, waits for a trigger and performs a finite acquisition. The task is then closed and the hardware is reconfigured then waits for the next trigger.

    This VI is attached for download at the beginning of this document.
  • Option 2:
    Use a Continuous Digital Input task with a external sample clock source. A counter will be used as a re-triggerable finite sample clock. The Digital Input task will then receive a finite number of sample clock edges, when these expire then the Counter re-arms.

    Counter Output:Gen Dig Pulse Train-Finite-Retriggerable.VI
    Digital Input: Cont Read Dig Chan-Ext Clk.VI

    The Counter Output example can be found in the NI Example Finder:
    Hardware Input/Output»DAQmx»Generating Digital Pulses» Generate Digital Pulse Train-Finite-Retriggerable.VI

    The Digital Input example can be found in the NI Example Finder:
    Hardware Input/Output»DAQmx»Digital Measurement»Cont Read Dig Chan-Ext Clk-.VI

 

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