I2C is a common communication protocol used in board level design for communication between processor and peripheral chips and components. It is based on a simple two wire synchronous protocol. Common communication rates are 100 and 400 kbps, but higher rates are now being used as well.
Using the FPGA on the RIO and CompactRIO hardware we can easily implement an I2C communication interface and integrate it with the rest of our application. This allows us to communicate with off-the-shelf components to extend the functionality of the RIO/CompactRIO hardware. It also allows us to use the RIO/CompactRIO hardware to automate and integrate chip and component design verification and test applications.
The examples are an implementation of a generic I2C communication master and a chip specific communication application. The chip specific example works with a MAXIM 518 Dual 8-bit DAC. The timing of the communication protocol is hardcoded using a number of Wait functions in the FPGA code and subVIs. It is currently set at 333 kHz, but can be adjusted by varying the Wait function settings.
The examples are not a complete implementation of the I2C protocol and should serve as a framework for a more complete implementation based on your requirements.
Signal Connections:
Connector0 DIO0 to I2C Clock
Connector0 DIO1 to I2C Data
The examples can easily be edited and recompiled for any of the RIO/CompactRIO targets. If you are using the cRIO-947x digital sourcing modules, you will need a few additional signal connections (pull down resistor, voltage source) to ensure the logic levels are correct.
