The LVDS standard defines the electrical characteristics of the transmitter and receiver of an LVDS interface. LVDS uses differential signals with low voltage swings to transmit data at high rates. Differential signals contrast to traditional single-ended signals in that two complementary lines are used to transmit a signal instead of one line. That is, two signals are generated of opposite polarity, and then the data transmission references the two signals to one another. This transmission scheme provides the kind of large common-mode rejection and noise immunity to a data transmission system that a single-ended system referenced only to ground cannot provide.
Figure 1 illustrates a typical LVDS transmitter. This transmitter consists of a current-mode driver, which provides around 3.5 mA of current through the transmission lines of the differential pair. At the receiver, a 100 Ω termination resistor is used to match the impedance of the transmission line that connects the receiver to the driver. Closely matching the impedance of this termination resistor with the impedance of the transmission lines reduces harmful signal reflections that decrease signal quality. The termination resistor also provides a path between the complementary signal paths of the system. The high input impedance of the receiver causes the 3.5 mA current coming from the driver to flow through the 100 Ω termination resistor, resulting in a voltage difference of 350 mV between the receiver inputs. As the path for the current within the driver changes from one path to another, the direction of the current flowing through the termination resistor at the receiver changes as well. The direction of the current through the resistor determines whether a positive or negative differential voltage is read. A positive differential voltage represents logic-high level, and a negative differential voltage represents logic-low level.
Figure 1. LVDS Driver and Receiver
As mentioned previously, the ANSI/TIA/EIA-644 standard provides a set of specifications to which all LVDS devices must adhere. Figure 2 shows a differential signal labeled with some of the key parameters defined by the standard.
Figure 2. Parameters of a Differential Signal
The first parameter is the differential output voltage (VOD). This voltage is the absolute value of the difference in voltage measured between the two output lines of the driver and is specified to be between 247 and 454 mV, with 350 mV being typical. VOH and VOL are voltage output high and voltage output low, respectively. These parameters are not specified for LVDS devices, but you can determine them by combining the output offset voltage range (VOS) with the differential output voltage (VOD). VOH and VOL are the output voltages of the driver with respect to ground and should always be within the input range of the receiver.
The standard defines the input voltage range of the receiver, VIN, to be 0 to 2.4 V. This input voltage range is significantly larger than the range of expected voltages from the driver. This difference provides the ability to absorb and reject common-mode noise, noise that is present on both lines of the differential pair, and allow for offsets between the driver and the receiver. Refer to Figure 3 for an illustration of this common-mode noise rejection.
Figure 3. Common-Mode Noise Rejection by the Receiver
The offset voltage is the common-mode voltage of the differential signal and is essentially the average voltage of the two lines of the differential pair with respect to ground. The minimum and maximum values for VOS according to the standard are 1.125 and 1.375 V. A typical value for VOS is 1.2 V. This value places the differential signal in the center of the voltage input range, VIN, for the receiver. With a voltage swing of 350 mV centered at 1.2 V, a margin of 1.025 V is available on each side of the signal. With this margin, the receiver effectively rejects common-mode noise and ground shifts within this margin.
Another important parameter is threshold voltage (VTH) of the receiver. The threshold voltage is the minimum difference in voltage between the lines of the differential signal that can be registered as a valid logic state. This voltage is specified as |100 mV|; therefore, the positive line of the differential pair must be at least 100 mV greater than the complementary line for the receiver to register logic high level, and the positive line must be at least 100 mV less than the complementary line for the receiver to register a logic low level. Compared to other differential technologies, LVDS and its derivative have some of the lowest voltage swings. This low voltage swing is one reason why LVDS can achieve very high data rates while consuming lower power than other available data transmission technologies. Smaller swings require less power and result in faster transition times between logic states, which is a key factor in the overall data bandwidth of a transmission path. ANSI/TIA/EIA-644 specifies that the maximum data throughput of a system is dependant on the transmission times of the signal. This relationship is expressed in a maximum output rise and fall time specification of 30% of the unit interval. For example, in order for a system to be classified as 1 Gb/s (unit interval of 1 ns), the signals must have rise and fall times smaller than 300 ps (30% of 1 ns). Refer to Figure 4 for a comparison of voltage swings for several common differential technologies.
Figure 4. Comparison of LVDS with Other Differential Technologies
Another feature defined by the LVDS standard is the LVDS fail-safe feature. In an LVDS interface, the fail-safe specification forces the receiver to provide logic-high level under certain input conditions. The receiver will output a logic high when one of the following conditions is true:
- The driver is disconnected from the receiver or powered off while the receiver is still powered on.
- The two lines of the differential pair become shorted.
- The inputs of the receiver are left open.
This fail-safe mode prevents the receiver from providing invalid data because of unexpected voltages on inputs.