Table Of Contents

PCI-5421 Pinout

Version:
    Last Modified: April 10, 2017

    Refer to the following figure and table for information about the PCI-5421 front panel connectors:

    Table 1. PCI-5421 Signal Descriptions
    Signal Connector Type Access Description
    CLK IN SMB Input Accepts an external PLL Reference Clock and can phase-lock the internal Sample Timebase Clock to the external Reference Clock. The signal on this connector can also be used as a Sample Clock source.
    PFI 0 Input/Output Accepts a trigger from an external source and can start or step through waveform generation or route signals from several clock, event, and trigger sources.
    PFI 1
    DIGITAL DATA & CONTROL (DDC) 68-pin male VHDCI Routes the 16-bit digital pattern outputs, digital pattern clock output, trigger outputs, trigger inputs, and a clock input.
    CH 0 SMB Output Generates waveforms from an analog output terminal.
    spd-note-note
    Note  

    The DDC connector is not available on the PCI-5421 8 MB memory option.


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