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PXIe-5172 PFI

    Last Modified: September 14, 2017

    The PXIe-5172 includes general purpose digital lines. You can connect to these resources through the front panel AUX I/O port using a supported cable and accessory, such as the SCB-19 (NI part number 783959-01). These signals are 3.3 V LVCMOS bidirectional digital signals and may be used in a variety of applications. Direction is controlled independently for each channel through the LabVIEW FPGA Module diagram

    The PFI signals are connected to the FPGA through 3.3 V LVCMOS buffers. These buffers allow for direction control, isolation to protect the FPGA from overvoltage conditions, and excellent signal quality through the matched 50 Ω output impedance. For exact I/O levels and input and output impedances, refer to the device specifications.

    The digital lines are protected against overvoltage conditions. The device provides this protection through a combination of diode clamps to the +3.3 V and GND lines and a positive temperature coefficient resistor for impedance matching.


    The interface from the PFI LVCMOS buffer to and from the FPGA is bidirectional. To guarantee that this line is not double-driven by both the FPGA and the buffer at the same time, the FPGA implements a direction control latency. This latency is an explicit delay between enabling the FPGA I/O buffer and setting the direction of the PFI. For more information on direction control latency, refer to the device specifications.

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