Generates the point-by-point value of a step signal.
Amplitude of the step signal.
Lower limit of the step signal.
Simulation time, in seconds, at which the output changes from offset to offset + amplitude.
Loop-cycle time or interval, in seconds, at which this node is called.
dt must be greater than zero.
Point-by-point value of the step signal.
The following equations define the step signal:
Where This Node Can Run:
Desktop OS: Windows
FPGA: This product does not support FPGA devices
Web Server: Not supported in VIs that run in a web application