Step Signal (G Dataflow)

Version:

Generates the point-by-point value of a step signal.

reset

A Boolean that specifies the initialization of the internal state of the node.

 True Initializes the internal state of the node by returning the output at time t = 0. False Does not initialize the internal state of the node.

Default: False

amplitude

Amplitude of the step signal.

Default: 1

offset

Lower limit of the step signal.

Default: 0

step time

Simulation time, in seconds, at which the output changes from offset to offset + amplitude.

Default: 0

dt

Loop-cycle time or interval, in seconds, at which this node is called.

dt must be greater than zero.

step output

Point-by-point value of the step signal.

Algorithm Definition for the Step Signal

The following equations define the step signal:

$y=\left\{\begin{array}{c}u\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\mathrm{if}\text{\hspace{0.17em}}t<\mathrm{step}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\mathrm{time}\\ u+a\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\mathrm{if}\text{\hspace{0.17em}}t\ge \mathrm{step}\text{\hspace{0.17em}}\mathrm{time}\end{array}$

where

• y is the step signal
• u is the lower limit of the step signal
• a is the amplitude of the step signal
• t is the current simulation time

Where This Node Can Run:

Desktop OS: Windows

FPGA: This product does not support FPGA devices

Web Server: Not supported in VIs that run in a web application