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Digital Pattern Generator (Ramp) (G Dataflow)

Last Modified: December 18, 2017

Generates a ramp digital waveform that contains a binary count-up pattern that starts at zero and counts up by one until it reaches 2n-1, where n equals the number of signals you specify.

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number of samples

The number of samples to include in the generated digital waveform.

Default: 256

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number of signals

The number of signals to include in the generated digital waveform.

Default: 8

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sample rate

The sample rate of the generated digital waveform.

Default: 1000

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digital waveform

The generated ramp pattern.

Where This Node Can Run:

Desktop OS: Windows

FPGA: This product does not support FPGA devices

Web Server: Not supported in VIs that run in a web application


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