Table Of Contents

Digital Pattern Generator (Ramp) (G Dataflow)

Version:
    Last Modified: April 3, 2017

    Generates a ramp digital waveform that contains a binary count-up pattern that starts at zero and counts up by one until it reaches 2n-1, where n equals the number of signals you specify.

    connector_pane_image
    datatype_icon

    number of samples

    The number of samples to include in the generated digital waveform.

    Default: 256

    datatype_icon

    number of signals

    The number of signals to include in the generated digital waveform.

    Default: 8

    datatype_icon

    sample rate

    The sample rate of the generated digital waveform.

    Default: 1000

    datatype_icon

    digital waveform

    The generated ramp pattern.

    Where This Node Can Run:

    Desktop OS: Windows

    FPGA: This product does not support FPGA devices


    Recently Viewed Topics