Generates a signal containing a periodic sinc pattern.
Amplitude of the pattern.
Shifts the pattern in the time axis.
Number of zero crossings between two adjacent peaks, which is equal to this input minus 1.
Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.
Default: No error
Sampling interval. This input must be greater than zero. If this input is less than or equal to zero, this node sets the output pattern to an empty array and returns an error.
Number of samples in the pattern. If this input is less than 1, the node sets the output pattern to an empty array and returns an error.
Output periodic sinc pattern.
Error information. The node produces this output according to standard error behavior.
If the sequence Y represents periodic sinc pattern, this node generates the pattern according to the following equation:
for i = 0, 1, 2, ..., N - 1
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported