Last Modified: January 9, 2017

Performs the DSSS spreading operation using the spreading code that you specify. The spreading code algorithm performs non-return-to-zero (NRZ) encoding of the **input bit stream** and the **spreading code**. However, the output is an array of zeros and ones.

The sequence of information bits to be spread.

The sequence of bits that determine how the bits in **input bit stream** are spread.

Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.

**Default: **no error

The sequence of data bits that is spread for transmission. The number of elements returned in this array equals the product of the **input bit stream** array length and the **spreading code** array length.

Each bit in the **input bit stream** is spread according to the following table.

Spreading Input | Spreading Output |
---|---|

0 | Spreading code |

1 | Complement of spreading code |

For example, an **input bit stream** array of 1100 and a **spreading code** value of 1010 return an **output chip stream** array of 0101 0101 1010 1010.

Direct Sequence Spread Spectrum (DSSS) is a process by which data is transmitted using a higher bandwidth signal as required by the data rate. Using DSSS allows multiple channels to occupy the same bandwidth, thus mitigating interference from other users at the expense of bandwidth expansion.

DSSS spreads each bit of signal data at the transmitter into *L* chips using a pseudorandom L-chip spreading code called a code word. The length *L* of the pseudorandom spreading code is also known as the bandwidth expansion factor because the chips are transmitted at a rate equal to *L * * bit rate of the data. The spreading code appears random to all receivers except the intended one, which uses the knowledge of the spreading code to demodulate and recover the transmitted information. Thus, multiple channels can occupy the same portion of the frequency spectrum by using code words that have little or no correlation with one another, and little or no autocorrelation for any shift other than zero.

Mathematically, a DSSS signal is described by

$y\left(t\right)={\displaystyle \underset{n=-\infty}{\overset{\infty}{\sum}}{\displaystyle \underset{m=0}{\overset{L-1}{\sum}}{a}_{n}{c}_{m}g(T-nT-m{T}_{c})}}$

where

y(T) is the transmitted DSSS signal

g(T) is the pulse-shaping signal of duration *T*_{c}

*a*_{n} is the n^{th} information bearing symbol

*c*_{m} is the m^{th} element of the L-long pseudorandom spreading code (also known as the chip sequence)

*T*_{c} is the chip period

T = L * T_{c} is the symbol period

**Where This Node Can Run: **

Desktop OS: Windows

FPGA: Not supported