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Parameter Port (Multirate Dataflow)

Last Modified: August 28, 2017

Imports parameter values to a Multirate diagram from a VI or another Multirate diagram.

Parameter ports enable you to create more dynamic diagrams by providing nodes with multiple possible sample count configurations. Parameter ports always generate the same value in a single diagram iteration but allow for different parameter values between diagram iterations.

Configure the domain of the parameter port to define a list of acceptable values that the port can import to the diagram. If the port receives a value outside of the domain and the diagram is targeted to the host, the port returns an error. If the port receives a value outside of the domain and the diagram is targeted to an FPGA, the port returns the first value listed in the domain.

On a Multirate diagram targeted to an FPGA, a parameter port imports parameter values from an FPGA VI using a FIFO. On a Multirate diagram targeted to the host, a parameter port imports parameter values directly from a host VI without using a FIFO.


Display Values

When editing the diagram, you can choose which display value, or value you want the port to generate, by enabling Execution Properties and clicking the diagram annotation beneath the parameter port. Changing the display value affects the displayed execution properties of nodes throughout the diagram and the displayed execution schedule for the entire diagram.

Use display values when editing your design to see how different parameter values affect diagram execution. However, note that display values do not affect the behavior of a deployed design because the parameter port generates whatever parameter value it imports from the calling VI or Multirate diagram.

Effects of Large Parameter Spaces

Avoid creating parameter domains with more values than are necessary for your design. When simulating or compiling a Multirate diagram, LabVIEW simulates or compiles the code for the entire parameter space. The parameter space includes every combination of parameter values from every parameter port domain on the diagram. Larger parameter spaces require greater amounts of FPGA resources and can slow performance when simulating or extend compile time.

Where This Node Can Run:

Desktop OS: Windows

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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