Create the following diagram to implement a line buffer for window-based image processing.
|Initialize the window.|
|Incoming pixels occupy the bottom right-most slot in their window.|
|Read a column from the delay line.|
|Append a pixel to a column in the delay line.|
|Shift the window and add the new column.|
|Update the delay line with the new column.|
|Filter the image based on your application needs. This example demonstrates computing the median of the image.|
Create this code in an FPGA VI within an Optimized FPGA Library. Use the FPGA VI on the diagram in a Clock-Driven Logic document and set the array input and output modes to Element-by-element on the Item tab. Using the element-by-element mode results in an initiation interval of one clock cycle.