Element-by-Element Array Processing with For Loops in Optimized FPGA VIs

The standard mode for processing array data works well in most cases and is the default mode for an Optimized FPGA VI. However, if your algorithm processes large arrays or if the data passing through the Optimized FPGA VI is costly to buffer in Clock-Driven Logic code, consider using the element-by-element mode to process array data.

If you select element-by-element mode for an Optimized FPGA VI that contains loops with multiple array inputs or outputs, the compiler alters the buffering and processing strategy depending on the scenario.

Buffering arrays results in better performance for data sets larger than 128 bits. The compiler buffers arrays in the following instances:

• Array inputs or outputs are wired to separate loops
  
• Any array is wired to a shift register
  

How the compiler processes array inputs informs how you order the input elements. The Optimized FPGA VI accepts an element of the array each time the ready for input signal is True.

Array Scenario	Processing Information
Multiple array inputs	The arrays are index-aligned, meaning that the compiler processes the first elements of all arrays on the same clock cycle, followed by the second elements of all arrays, and so on.
Array inputs mixed with scalar inputs	You must provide the scalar inputs on the same clock cycle as the first elements of the array inputs.
Array inputs of different sizes	The compiler ignores the appropriate out-of-index values for the smaller arrays, meaning it does not matter what values you provide during these clock cycles.
Auto-indexing mismatched arrays on the same loop	The number of elements that the compiler processes for each array is equal to the maximum number of executions for the loop. In the following example, the compiler processes three elements for each array because the For Loop iterations adjust to the size of the smallest auto-indexing array. The compiler ignores the last five elements of the larger array.

How the compiler processes array outputs informs how you receive the output elements. The Optimized FPGA VI produces an element for each output array each time the output valid signal is True.

Array Scenario	Processing Information
Multiple array outputs	The arrays are index-aligned, meaning that the compiler generates the first elements of all arrays on the same clock cycle, followed by the second elements of all arrays, and so on.
Array outputs mixed with scalar outputs	The scalar outputs generate valid data on the same clock cycle that generates the last element of the largest array output.
Array outputs of different sizes	The out-of-index data that generates from smaller arrays is not valid for clock cycles beyond the size of the array.