Testing Communication between the Host VI and an FPGA VI

Download Manual | Offline Viewer Required

Version:

Last Modified: January 11, 2018

To complete this task, you'll need the FPGA VI and the host VI you want to communicate between.

You can run FPGA code on the host computer to test the logic of the code without investing the time to compile it. Testing the communication between the host VI and the FPGA VI, on the host computer, saves time and makes it easier to repeat tests until you're ready to deploy to the FPGA.

What to Use

What to Do

Create the following diagram to communicate with the FPGA VI from a host VI.

Customize the gray sections for your unique programming goals.

	To specify the FPGA bitfile you want to deploy to the target, complete the following steps: On the diagram, select Open FPGA VI Reference. On the Item tab, in the Properties section, select Deploy from project or Deploy from file. Depending on which mode you selected in the previous step, either select or wire the bitfile you want to run. Wire the address of the FPGA target to RIO address. When you run this host VI, a reference to the FPGA VI associated with the bitfile you selected opens and runs on the FPGA target you specify.
	When testing communication between a host VI and the FPGA VI, use test code that mirrors the communication that you want to occur when you actually deploy the FPGA VI. Use the FPGA Host Interface nodes to communicate with code on an FPGA and in simulation on the host computer. In the diagram above, one of the ways the host VI and the FPGA VI communicates is through a DMA FIFO using the Write DMA FIFO and Read DMA FIFO nodes. When this host VI runs, the host VI and the FPGA VI write data to and read data from a block of memory on the host that simulates a FIFO on the FPGA. Note The host VI cannot simulate FPGA Host Interface nodes that perform hardware-specific functions, such as the Download FPGA VI node or the P2P Streaming nodes.
	Use the Close FPGA VI Reference node to close every reference the Open FPGA VI Reference node creates. If you don't close the reference, the FPGA VI runs indefinitely until you click the Abort button in the FPGA VI.