The target selector displays the targets on which a document exists, as well as any associated build name. The display format is Target Name (Build Name). Documents with no build name display only Target Name.
Only the following documents types have build names for their build outputs, defined in SystemDesigner on the Item tab for the targeted document:
A top-level FPGA VI, for the bitfile
An Optimized FPGA VI
Use the target selector on the Document toolbar to navigate between instances of the same document in multiple locations in your project hierarchy.
The following image and tasks walk you through an exercise to identify elements in the editor that affect what you see in the target selector.
- Place documents on the target. In this example, there are two targets, Unit A and Unit B. Each target contains an instance of the same four documents.
- Select a top-level VI on the target. A top-level VI could be a top-level FPGA VI or an Optimized FPGA VI. In this example, Conditional Disable Structure Top Level with Offset is selected.
- Specify a build name for the bitfile of a top-level FPGA VI. In this example, the build name for the VI selected on Unit A is BitfileAOffset. For an Optimized FPGA VI, LabVIEW automatically uses the VI name as the build name.
- Use symbols to differentiate between builds. You can create and define user-defined symbols for each build. You can also use target-defined symbols. In this example, the symbol Offset is 2 for the VI selected on Unit A.
Top-Level VIs in the Target Selector
Optimized FPGA VIs and top-level FPGA VIs can each serve as a top-level VI where other VIs are called on their diagrams. The following image displays a top-level FPGA VI on multiple targets with different build names.
- In this top-level FPGA VI, the target selector shows that the VI is targeted to USRP Unit A and USRP Unit B. It also displays the specific build names, BitfileAOffset and BitfileBOffset.
Subdocuments in the Target Selector
In documents used as a subVI, subCDL, or subMRD within a top-level VI, the target selector displays the target and any associated build name the subVI is used within.
Disable Structures and the Target Selector
You can create custom condition symbols targeted to a top-level FPGA VI and use these symbols in any Disable Structure within your FPGA application. The following image demonstrates a Clock-Driven Logic (CDL) document that uses a Disable Structure and conditional symbols to enable or disable a diagram in the structure depending on the top-level FPGA VI the CDL document is called from.
- The target selector for the CDL document displays all the contexts in which the file exists, using the format TargetName (BuildName). In this example, the CDL document exists in six contexts: each USRP, and then each top-level FPGA VI.
- The diagram that executes when the user-defined symbol, Offset, is defined as 2. When Offset is defined as 2, all other diagrams in the Disable Structure will not execute.
- This Disable Structure contains subdiagrams for 0, 2, and 5. The top-level FPGA VI that calls this CDL document defines that Offset value in SystemDesigner and determines which diagram runs within that top-level FPGA VI.