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Disable Structure (Clock-Driven Logic)

    Last Modified: April 28, 2017

    Contains one or more subdiagrams, or cases, of which only the Enabled subdiagram executes. You can conditionally disable subdiagrams using the Edit Condition for Active Subdiagram button on the Item tab.


    Case Selector Label

    Part of the structure that displays the value(s) for which the associated case executes. You also can use the case selector label to specify a default case.



    Point through which data enters or exits a structure.

    Disabling Subdiagrams Based on a Specified Condition

    Select Edit Condition for Active Subdiagram in the Item tab to set one or more conditions that, when met, enables a subdiagram in the Disable Structure. An example of when you might conditionally enable a subdiagram is to run code only on a specific target.

    Refer to the following table for a list of available condition symbols and their values.


    Symbol values are case-sensitive strings. As a result, numeric values are handled as strings rather than numbers. For example, if you define the value of a custom symbol as 0.0 and then set the condition to 0 in the Disable Structure subdiagram, that condition evaluates to false.

    Condition Symbol Valid Values Description
    • ARM
    • x64
    The processor on which the subdiagram executes.
    • Linux
    • Win
    The operating system on which the subdiagram executes.
    • 32
    • 64
    The bitness of the application that executes the subdiagram.
    • FPGA
    • RT
    • Windows
    The platforms or targets on which the subdiagram executes.
    • KINTEX7
    The FPGA family on which the subdiagram executes.
    The location where the subdiagram executes: on the FPGA target or on the development computer in simulation.
    • USRP_294XR__295XR_200_MSPS
    • USRP_294XR__295XR_120_MSPS
    • PXIE_7975R
    • PXIE_7976R
    The target class of the FPGA target on which the subdiagram executes.

    When you select an FPGA VI in SystemDesigner, the symbol values for that FPGA target are listed under the Compile Symbols section of the Item tab. You can only access these symbols on a VI that is targeted to an FPGA.

    Search LabVIEW for the following installed examples:
    • Diagram Disable Structure
    • Conditional Disable Structure

    Where This Node Can Run:

    Desktop OS: none

    FPGA: All devices

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