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AXI Video Direct Memory Access (Clock-Driven Logic)

Last Modified: August 28, 2017

Provides an interface for controlling and synchronizing video frame stores from external memory.

You can link together Multiple VDMAs from different clock domains to control frame buffer reads and writes from multiple sources. This node performs automatic frame skips and repeats to seamlessly allow frame rate conversion. Support for up to 32 external frame buffers with image sizes of 4k × 4k is provided. The core is programmable through a register interface for setting and controlling frame synchronization (can be turned on/off in real-time), frame read/write delays, source synchronization switching, circular buffer enable, and more using logic or a microprocessor. Error interrupt status bits are provided for processor monitoring.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

Interface: AXI4, AXI4-Stream

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Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application


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