Digital Gain - 4 spc (Clock-Driven Logic)

Digitally controls the I and Q levels.

You must use this node inside a Clock-Driven Loop. This node provides the following functionality: $\text{data out.I}\le \text{data in.I}\times \text{gain I data out.Q}\le \text{datain.Q}\times \text{gainQ}$, where $\times$ represents scalar multiplication.

Samples Per Cycle (SPC)—On the Item tab, change the number of parallel samples used on the data in and data out terminals. For multiple samples per cycle, data in and data out become fixed size arrays of SPC elements. The first element, data[0], is the oldest sample in the array.

Overflows—Gain values greater than 1.0 (or less than or equal to -1.0) may cause overflows (signal clipping) to occur. Overflows on data in.overflow are pipelined along with the data path, combined with overflows that occur inside this node, and output on data out.overflow.

Reset—Toggling the reset input high resets the registers in the output valid path, allowing for deterministic startup behavior. The registers in the data out path are not reset; however, output valid is held low while reset is asserted and does not assert after reset until the registers in the data out path have been flushed. While reset is asserted, ready for input is held low and input valid is ignored.

Pipeline delay	4 clock cycles
Approximate resource usage in a Xilinx Virtex-5 FPGA or Virtex-6 FPGA	Slice flip-flops: 500 Slice LUTs: 650 Block RAMs (18kb): 0 DSP48E(1)s: 8
Approximate maximum clock rate in a Xilinx Virtex-5 FPGA or Virtex-6 (-1) FPGA	160 MHz