From 6:00 PM CST Friday, Feb 15th - 2:00 AM CST Sunday, Feb 17th, will be undergoing system upgrades that may result in temporary service interruption.

We appreciate your patience as we improve our online experience.

Table Of Contents

Read Register (Clock-Driven Logic)

Last Modified: August 28, 2017

Reads a single value from a register on the FPGA target.


reference in

A reference to a register item.


reference out

A reference to a register item.



The data read from memory on the FPGA target. If you have not written data to the register item, the data value is undefined.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

Recently Viewed Topics