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Peek FIFO (Clock-Driven Logic)

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    Last Modified: September 14, 2017

    Returns the top element of a FIFO without removing it.

    Peek FIFO is supported on all local, DMA host-to-target, and peer-to-peer reader FIFOs, regardless of the implementation type.

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    Note  

    Peek FIFO must be in the same clock domain as the Read FIFO node. Otherwise, the program returns a code generation error when you try to compile the FPGA VI.

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    reference in

    The FIFO on which the node peeks, or returns without removing.

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    error in

    Error conditions that occur before this node runs.

    The node responds to this input according to standard error behavior.

    Standard Error Behavior

    Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

    error in does not contain an error error in contains an error
    If no error occurred before the node runs, the node begins execution normally.

    If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

    If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

    Default: No error

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    ready for output

    Boolean value that specifies whether downstream nodes are ready for this node to return a new value.

    Use Feedback Node to wire ready for input of a downstream node to ready for output of the current node. If this input is False during a given cycle, output valid returns False during that cycle.

    True The downstream node is ready for the next data point.
    False The downstream node is not ready for the next data point.

    Default: False

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    reference out

    A reference to the FIFO that this node peeks at, or returns without removing.

    reference out returns the value wired to reference in.

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    data

    The oldest data element in the FIFO. If the FIFO is empty, data returns an undefined element.

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    error out

    Error information.

    The node produces this output according to standard error behavior.

    Standard Error Behavior

    Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

    error in does not contain an error error in contains an error
    If no error occurred before the node runs, the node begins execution normally.

    If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

    If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.
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    output valid

    Boolean value that indicates whether this node computes a result that downstream nodes can use.

    Wire this output to input valid of a downstream node to transfer data from the node to the downstream node.

    True Downstream nodes can use the result this node computes.
    False This node returns an undefined value that downstream nodes cannot use.
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    Note  

    This node may return different undefined values when executed in simulation mode versus when executed on hardware.

    Handshake Protocol

    Because this node may return invalid data in certain cases, such as when the FIFO is being cleared or the FIFO is currently empty, this node uses the 4-wire handshake protocol to alert you if this node returns invalid data. Check the status of output valid to ensure the data output is valid.

    Where This Node Can Run:

    Desktop OS: none

    FPGA: All devices

    Web Server: Not supported in VIs that run in a web application


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