Table Of Contents

Index Array (G Dataflow)

Last Modified: January 23, 2017

Returns the value stored in an array at a specified index.

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array

An n-dimensional array of any type.

If array is an empty array, element returns the default value of the defined data type for the array.

This input also accepts waveforms.

Data Type Changes on FPGA

When you add this node to a document targeted to an FPGA, this input has a default data type that uses fewer hardware resources at compile time.

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index

A number that refers to a location within the input array.

This node automatically provides an index input for each dimension of the array.

Behavior for Out of Range Values

If the index is less than zero or greater than the length of array in this dimension, this node returns the default value of the defined data type for the array.

Which Index Refers to Which Dimension?

Array nodes in LabVIEW access array data in row-major order. In a 2D array, row is the first, major index. Column is the last, minor index. In bigger multidimensional arrays, column remains the last index and the more major indexes are added to the front. Thus, vol is the first index, followed by page, row, and column. These names are index identifiers and have no other meaning.

Unwired Index Inputs

Unwired index inputs allow you to retrieve a subarray of the array rather than a single element. For example, to retrieve column 1 of a 2D array, specify 1 in the column index and leave the row index unwired.

How Does index Relate to Multiple element or subarray Outputs?

If you expand the node to show more than one element or subarray output, LabVIEW provides a set of index inputs for each output. The values you wire to a set of index inputs determine the value of the corresponding output. However, if you do not wire values to a set of index inputs, the corresponding element or subarray output returns the element or subarray that follows the previous element or subarray output in the original array. Refer to the Examples tab for an illustration of this relationship.

Default: 0

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element

The value stored in array at the specified index. This output is the same type as the elements of array.

Data Type Changes on FPGA

When you add this node to a document targeted to an FPGA, this input has a default data type that uses fewer hardware resources at compile time.

Resizing Behavior

When you wire an array to this node, the node resizes automatically to display index inputs for each dimension in the array you wire to array. You also can add additional element terminals by resizing the node.

Accessing a Subarray by Disabling Indexing along a Dimension

You can disable indexing along a dimension by leaving the corresponding index input unwired, unless you are indexing a 1D array. By default, the first dimension has indexing enabled, with the others disabled. You can wire a constant or control to the index inputs that you want enabled.

For example, if you want to index a row in a 2D array, the first index input is enabled and the second index input is disabled. If you want to index that same 2D array also by column, you can resize the function to show another set of input terminals. This next set of inputs has its own corresponding element output. By default, if you do not wire any index input terminals, the first element indexes row 0, the second element indexes row 1, and so on.

The following image illustrates this node's behavior for a variety of inputs:

Output Value Comments
element, all indexes wired 1
subarray, row wired [1, 1, 1] Without a value for the column dimension, Index Array returns the entire row specified by the row input.
subarray, indexes unwired [2, 2, 2] This output has no values specified for its corresponding row and column inputs. Therefore, the function returns the subarray that immediately follows the previous output.
subarray, column wired [0, 1, 2] Without a value for the row dimension, Index Array returns the entire column specified by the column input.

Where This Node Can Run:

Desktop OS: Windows

FPGA: All devices (only within an Optimized FPGA VI)


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