Table Of Contents

Configure DMA FIFO (G Dataflow)

Last Modified: June 1, 2017

Specifies the capacity, or depth, in elements of the host-side FIFO of the DMA channel.

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reference in

A reference to an FPGA VI.

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depth

Number of elements specified for the host-side FIFO of the DMA channel.

Default: 0

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reference out

Reference to an FPGA VI.

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actual depth

The number of elements in the host FIFO of the DMA buffer.

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error in

Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.

Default: No error

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error out

Error information. The node produces this output according to standard error behavior.

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported


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