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Using a Ping Pong Memory Implementation to Increase the Throughput of an Optimized FPGA VI

Last Modified: September 20, 2016

Ping pong, or double buffer, memory implementations tend to increase the throughput of an Optimized FPGA VI as compared to single buffer memory implementations, especially for VIs that include cascading loops.

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Note  

The following statistics are for instructional purposes only. Exact results may vary.

In the following single buffer example, the first For Loop processes the input array using SubVI 1, and the second For Loop processes the resulting array using SubVI 2. If the input array size is 32 elements, the Optimized FPGA VI achieves an initiation interval of 64 clock cycles because the Optimized FPGA VI processes the arrays sequentially. Therefore, the first loop does not accept new inputs until the second loop finishes processing the array, and at one clock cycle per array element, the result is an initiation interval of 64 clock cycles.

You can achieve an initiation interval that is half as long by using a ping pong memory implementation, which doubles the size of the array and allows the loops to process separate halves of the array simultaneously.

What to Use

What to Do

Create the following diagram to implement a ping pong memory implementation for the example VI.

Customize the gray sections for your unique programming goals.

Create code to process the array. In this example, two different VIs process the array.
Specify the array indexing pattern your programming goal requires. In this example, the array is indexed by decrementing the iteration terminal by one.
Create the ping pong array indexing pattern code, as shown in the following image.

In this example, the PingPongAddr subVI returns the array address when Ping? is True, and a value of -1 when the address is out of bounds.
Double the size of the array to allow the loops to process separate halves of the array simultaneously.

Create ping pong toggles to select which half of the array each loop processes. Consecutive iterations of the Optimized FPGA VI use either the lower half or the upper half of the array, depending on the logic of the toggles.

In this example, the first loop processes data using half of the array during one iteration of the Optimized FPGA VI. In the next iteration, the second loop processes data using the remaining half of the array. Because both loops are processing the array at the same time, the initiation interval is 32 clock cycles.


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