Table Of Contents

Changes to the Editor for Optimized FPGA VIs

Last Modified: March 30, 2016

When you open an Optimized FPGA VI, the editor adds and removes certain features to help you scope your code and determine if performance and resource directives can be met on the FPGA.

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Note  

The Optimized FPGA VI designation is stored in SystemDesigner, and you should open the Optimized FPGA VI from there. If you open the VI from the Project Files tab, which does not have the stored designation, you might not benefit from the restrictions and guidance of the Optimized FPGA VI-specific editor changes.

The following image highlights the key changes to the editor when developing Optimized FPGA VIs.

  1. The FPGA Estimates button allows you to specify performance and resource directives and then provides data on whether your code can meet the performance and resource directives you specified.
  2. Optimized FPGA VI development focuses on creating algorithms that provide the compiler the best opportunity to optimize the code within it. Therefore, not every node available in G Dataflow is available in an Optimized FPGA VI. For example, the palette in an Optimized FPGA VI does not include nodes for creating or accessing resources like FIFOs or memory.
  3. The data generated when you click the FPGA Estimates button displays in the Algorithm Estimates tab. Deployment errors and warnings display during development in the Errors & Warnings tab to call attention to code that will not work on hardware.

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