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Viterbi Decoder (Clock-Driven Logic)

Last Modified: September 10, 2016

Implements a fully synchronous Viterbi decoder, using a single clock.Options include parameterizable constraint length, convolutional codes, and traceback length. You can use various architectures including parallel, serial, multi-channel, and dual decoding. The core is delivered through the Xilinx CORE Generator System and integrates with the Xilinx design flow.

In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: Yes

Interface: AXI4-Stream

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Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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