Table Of Contents

Read Memory (Clock-Driven Logic)

Last Modified: September 10, 2016

Reads from memory available on the FPGA target. If the memory is configured for both read and write access, you can only read from interface [A]. If you configure the memory for dual port read access, you may access interface [A] or [B].

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reference in

A reference to a memory item.

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address

The memory address to read from.

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reference out

A reference to the memory item.

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data

The data retrieved from the specified address of the memory item.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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