# Norm Square (Clock-Driven Logic)

Computes the norm square of a vector.

## x

The matrix to manipulate.

## input valid

A Boolean that describes whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

 TRUE The next data point has arrived for processing. FALSE The next data point has not arrived for processing.

A Boolean that defines whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.

 True Downstream nodes are ready for this node to return a new value. False Downstream nodes are not ready for this node to return a new value.
Note

If this input is False during a given cycle, the output valid output returns False during that cycle.

Default: True

## norm square

The norm square of the input vector.

## operation overflow

A Boolean that indicates whether the theoretical computed value exceeds the valid range of the output data type.

 TRUE The theoretical computed value exceeds the valid range of the output data type. FALSE The theoretical computed value does not exceed the valid range of the output data type.

## output valid

A Boolean that indicates whether this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

 True The node has computed a result that downstream nodes can use. False This node has not computed a result that downstream nodes can use. Any data output returns an undefined value. The undefined value returned by a data output may differ between simulation and hardware.

A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

 True The node is ready to accept new input data. False The node is not ready to accept new input data.
Note

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices