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CORDIC (Clock-Driven Logic)

Last Modified: September 10, 2016

Generates the generalized coordinate rotational digital computer (CORDIC) algorithm that iteratively solves trigonometric, hyperbolic, and square root equations. The core is fully synchronous using a single clock and has AXI4 Stream compliant interfaces. Options include parameterizable data width. The core supports either serial architecture for minimal area implementations or parallel architecture for speed optimization. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow.

In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

Interface: AXI4-Stream

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Where This Node Can Run:

Desktop OS: none

FPGA: All devices


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